Lines Matching refs:firmware
27 #include <linux/firmware.h>
249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
250 uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;
251 uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi;
287 offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;
438 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
445 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
454 adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].ucode_id = AMDGPU_UCODE_ID_VCE;
455 adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw;
456 adev->firmware.fw_size +=
458 DRM_INFO("PSP loading VCE firmware\n");
504 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
565 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
612 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
648 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
649 tmr_mc_addr = (uint64_t)(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi) << 32 |
650 adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;
669 offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;
843 /* This function enables MGCG which is controlled by firmware.
845 accessible but the firmware will throttle the clocks on the