amd/amdgpu/sdma_v6_0.c

182 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
186 		if (sdma && sdma->burst_nop && (i == 0))
340 	for (i = 0; i < adev->sdma.num_instances; i++) {
376 		for (i = 0; i < adev->sdma.num_instances; i++) {
406 	for (i = 0; i < adev->sdma.num_instances; i++) {
432 	for (i = 0; i < adev->sdma.num_instances; i++) {
433 		ring = &adev->sdma.instance[i].ring;
502 						      adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
510 		/* Set up sdma hang watchdog */
595 	if (!adev->sdma.instance[0].fw)
604 		hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
609 			(adev->sdma.instance[0].fw->data +
624 			(adev->sdma.instance[0].fw->data +
636 		for (i = 0; i < adev->sdma.num_instances; i++) {
638 			hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
643 				(adev->sdma.instance[0].fw->data +
654 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
660 				(adev->sdma.instance[0].fw->data +
671 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
686 	for (i = 0; i < adev->sdma.num_instances; i++) {
721 	for (i = 0; i < adev->sdma.num_instances; i++) {
722 		ring = &adev->sdma.instance[i].ring;
763 	/* enable sdma ring preemption */
1090 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1096 		if (sdma && sdma->burst_nop && (i == 0))
1210 		adev->sdma.ras = &sdma_v6_0_3_ras;
1245 			      &adev->sdma.trap_irq);
1249 	for (i = 0; i < adev->sdma.num_instances; i++) {
1250 		ring = &adev->sdma.instance[i].ring;
1262 		sprintf(ring->name, "sdma%d", i);
1264 				     &adev->sdma.trap_irq,
1272 		dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1284 	for (i = 0; i < adev->sdma.num_instances; i++)
1285 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1331 	for (i = 0; i < adev->sdma.num_instances; i++) {
1449 		DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1457 			amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1548 	for (i = 0; i < adev->sdma.num_instances; i++) {
1549 		adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1550 		adev->sdma.instance[i].ring.me = i;
1565 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1566 					adev->sdma.num_instances;
1567 	adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1568 	adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1636 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1651 	for (i = 0; i < adev->sdma.num_instances; i++) {
1653 			&adev->sdma.instance[i].ring.sched;
1655 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;