amd/amdgpu/sdma_v4_4_2.c

307  * @ib: IB object to schedule
314 				   struct amdgpu_ib *ib,
325 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
326 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
327 	amdgpu_ring_write(ring, ib->length_dw);
1010 	struct amdgpu_ib ib;
1024 	memset(&ib, 0, sizeof(ib));
1026 					AMDGPU_IB_POOL_DIRECT, &ib);
1030 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1032 	ib.ptr[1] = lower_32_bits(gpu_addr);
1033 	ib.ptr[2] = upper_32_bits(gpu_addr);
1034 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1035 	ib.ptr[4] = 0xDEADBEEF;
1036 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1037 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1038 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1039 	ib.length_dw = 8;
1041 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1059 	amdgpu_ib_free(adev, &ib, NULL);
1070  * @ib: indirect buffer to fill with commands
1077 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1083 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1085 	ib->ptr[ib->length_dw++] = bytes - 1;
1086 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1087 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1088 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1089 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1090 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1097  * @ib: indirect buffer to fill with commands
1105 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1111 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1113 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1114 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1115 	ib->ptr[ib->length_dw++] = ndw - 1;
1117 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1118 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1126  * @ib: indirect buffer to fill with commands
1135 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1141 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1142 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1143 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1144 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1145 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1146 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1147 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1148 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1149 	ib->ptr[ib->length_dw++] = 0;
1150 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1157  * @ib: indirect buffer to fill with padding
1159 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1165 	pad_count = (-ib->length_dw) & 7;
1168 			ib->ptr[ib->length_dw++] =
1172 			ib->ptr[ib->length_dw++] =
1944  * @ib: indirect buffer to copy to
1954 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1960 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1963 	ib->ptr[ib->length_dw++] = byte_count - 1;
1964 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1965 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1966 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1967 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1968 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1974  * @ib: indirect buffer to copy to
1981 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1986 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1987 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1988 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1989 	ib->ptr[ib->length_dw++] = src_data;
1990 	ib->ptr[ib->length_dw++] = byte_count - 1;