Lines Matching defs:adev
36 static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev,
40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];
166 static void sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev,
187 dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n",
195 static int sdma_v4_4_query_ras_error_count_by_instance(struct amdgpu_device *adev,
204 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);
208 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value,
211 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);
215 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,
236 static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev)
242 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
243 for (i = 0; i < adev->sdma.num_instances; i++) {
244 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER);
246 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2);
252 static void sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status)
256 for (i = 0; i < adev->sdma.num_instances; i++) {
257 if (sdma_v4_4_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
258 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);