amd/amdgpu/sdma_v2_4.c

114 	for (i = 0; i < adev->sdma.num_instances; i++)
115 		amdgpu_ucode_release(&adev->sdma.instance[i].fw);
146 	for (i = 0; i < adev->sdma.num_instances; i++) {
151 		err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
154 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
155 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
156 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
157 		if (adev->sdma.instance[i].feature_version >= 20)
158 			adev->sdma.instance[i].burst_nop = true;
163 			info->fw = adev->sdma.instance[i].fw;
173 		for (i = 0; i < adev->sdma.num_instances; i++)
174 			amdgpu_ucode_release(&adev->sdma.instance[i].fw);
223 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
227 		if (sdma && sdma->burst_nop && (i == 0))
340 	for (i = 0; i < adev->sdma.num_instances; i++) {
380 	for (i = 0; i < adev->sdma.num_instances; i++) {
405 	for (i = 0; i < adev->sdma.num_instances; i++) {
406 		ring = &adev->sdma.instance[i].ring;
468 	for (i = 0; i < adev->sdma.num_instances; i++) {
469 		ring = &adev->sdma.instance[i].ring;
733 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
739 		if (sdma && sdma->burst_nop && (i == 0))
814 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;
836 			      &adev->sdma.trap_irq);
842 			      &adev->sdma.illegal_inst_irq);
848 			      &adev->sdma.illegal_inst_irq);
852 	for (i = 0; i < adev->sdma.num_instances; i++) {
853 		ring = &adev->sdma.instance[i].ring;
856 		sprintf(ring->name, "sdma%d", i);
857 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
873 	for (i = 0; i < adev->sdma.num_instances; i++)
874 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1046 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1059 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1084 		drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1152 	for (i = 0; i < adev->sdma.num_instances; i++) {
1153 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1154 		adev->sdma.instance[i].ring.me = i;
1169 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1170 	adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1171 	adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1238 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1254 	for (i = 0; i < adev->sdma.num_instances; i++) {
1256 			&adev->sdma.instance[i].ring.sched;
1258 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;