amd/amdgpu/nbio_v2_3.c

232 	uint32_t def, data;
237 	def = data = RREG32_PCIE(smnCPM_CONTROL);
239 		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
246 		data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
254 	if (def != data)
255 		WREG32_PCIE(smnCPM_CONTROL, data);
261 	uint32_t def, data;
266 	def = data = RREG32_PCIE(smnPCIE_CNTL2);
268 		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
272 		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
277 	if (def != data)
278 		WREG32_PCIE(smnPCIE_CNTL2, data);
284 	int data;
287 	data = RREG32_PCIE(smnCPM_CONTROL);
288 	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
292 	data = RREG32_PCIE(smnPCIE_CNTL2);
293 	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
334 	uint32_t def, data;
336 	def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
337 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
338 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
340 	if (def != data)
341 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
355 	uint32_t def, data;
357 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
361 		data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
363 		data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
366 			data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
368 			data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
370 		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
373 		data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
375 		data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
377 		data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
380 	if (def != data)
381 		WREG32_PCIE(smnPCIE_LC_CNTL, data);
387 	uint32_t def, data;
391 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);
392 	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
393 	if (def != data)
394 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data);
396 	def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
397 	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
398 	if (def != data)
399 		WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
401 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
402 	data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
403 	if (def != data)
404 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
411 	uint32_t def, data;
413 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
414 	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
415 	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
416 	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
417 	if (def != data)
418 		WREG32_PCIE(smnPCIE_LC_CNTL, data);
420 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
421 	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
422 	if (def != data)
423 		WREG32_PCIE(smnPCIE_LC_CNTL7, data);
425 	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
426 	data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
427 	if (def != data)
428 		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
430 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
431 	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
432 	if (def != data)
433 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);
435 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
436 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
437 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
438 	if (def != data)
439 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
441 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
442 	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
443 	if (def != data)
444 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
446 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
447 	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
448 	if (def != data)
449 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
453 	def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
454 	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
456 	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
457 	if (def != data)
458 		WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
460 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
461 	data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
463 	if (def != data)
464 		WREG32_PCIE(smnPCIE_LC_CNTL6, data);
471 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
472 	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
473 	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
474 	if (def != data)
475 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
477 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
478 	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
479 	if (def != data)
480 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
482 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
483 	data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
485 		data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
487 		data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
488 	data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
489 	if (def != data)
490 		WREG32_PCIE(smnPCIE_LC_CNTL, data);
492 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
493 	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
494 	if (def != data)
495 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);
513 	 * Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data)