Lines Matching refs:tmp
114 uint32_t tmp;
163 tmp = RREG32_SOC15_OFFSET(
166 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
171 tmp);
177 uint32_t tmp;
180 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
184 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
186 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
188 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
190 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
192 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
194 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
198 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
203 uint32_t tmp;
206 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
208 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
210 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
213 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
215 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
217 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
219 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
222 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
224 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
226 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
228 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
231 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
233 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
235 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
236 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
239 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
240 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
244 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
246 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
247 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
249 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
252 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
258 uint32_t tmp;
260 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
262 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
263 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
264 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
267 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
299 uint32_t tmp;
310 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
312 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
314 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
317 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
319 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
322 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
324 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
326 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
328 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
330 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
332 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
336 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
341 i * hub->ctx_distance, tmp);
408 u32 tmp;
420 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
423 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
425 tmp = REG_SET_FIELD(tmp,
430 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
433 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
435 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
438 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
452 u32 tmp;
456 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
459 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
462 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
465 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
468 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
471 tmp = REG_SET_FIELD(tmp,
475 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
478 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
481 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
484 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
487 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
490 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
494 tmp = REG_SET_FIELD(tmp,
497 tmp = REG_SET_FIELD(tmp,
504 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);