amd/amdgpu/mmhub_v2_3.c

79 mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
90 	dev_err(adev->dev,
93 	switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
103 	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
105 	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
108 	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
111 	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
114 	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
117 	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
120 static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
124 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
133 static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev)
135 	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
137 	mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base);
140 		     (u32)(adev->gmc.gart_start >> 12));
142 		     (u32)(adev->gmc.gart_start >> 44));
145 		     (u32)(adev->gmc.gart_end >> 12));
147 		     (u32)(adev->gmc.gart_end >> 44));
150 static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
157 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
158 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
162 		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
164 		     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
167 	value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
175 		     (u32)(adev->dummy_page_addr >> 12));
177 		     (u32)((u64)adev->dummy_page_addr >> 44));
185 static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev)
204 static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
228 	if (adev->gmc.translate_further) {
249 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
261 static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
281 static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
283 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
291 				    adev->vm_manager.num_level);
309 				    adev->vm_manager.block_size - 9);
313 				    !adev->gmc.noretry);
322 				    lower_32_bits(adev->vm_manager.max_pfn - 1));
325 				    upper_32_bits(adev->vm_manager.max_pfn - 1));
331 static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
333 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
346 static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
348 	if (amdgpu_sriov_vf(adev)) {
355 			     adev->gmc.vram_start >> 24);
357 			     adev->gmc.vram_end >> 24);
361 	mmhub_v2_3_init_gart_aperture_regs(adev);
362 	mmhub_v2_3_init_system_aperture_regs(adev);
363 	mmhub_v2_3_init_tlb_regs(adev);
364 	mmhub_v2_3_init_cache_regs(adev);
366 	mmhub_v2_3_enable_system_domain(adev);
367 	mmhub_v2_3_disable_identity_aperture(adev);
368 	mmhub_v2_3_setup_vmid_config(adev);
369 	mmhub_v2_3_program_invalidation(adev);
374 static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
376 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
402  * @adev: amdgpu_device pointer
405 static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
448 static void mmhub_v2_3_init(struct amdgpu_device *adev)
450 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
492 mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
500 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
526 mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
535 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
569 static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
572 	if (amdgpu_sriov_vf(adev))
575 	mmhub_v2_3_update_medium_grain_clock_gating(adev,
577 	mmhub_v2_3_update_medium_grain_light_sleep(adev,
583 static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u64 *flags)
587 	if (amdgpu_sriov_vf(adev))