45 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
63  * Set ring and irq function pointers
88 	struct amdgpu_ring *ring;
111 			ring = &adev->jpeg.inst[i].ring_dec[j];
112 			ring->use_doorbell = true;
113 			ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
115 				ring->doorbell_index =
120 					ring->doorbell_index =
124 					ring->doorbell_index =
128 			sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
129 			r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
178 	struct amdgpu_ring *ring;
213 			ring = &adev->jpeg.inst[i].ring_dec[j];
217 			MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
219 			MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));
221 			MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
298 	struct amdgpu_ring *ring;
308 				ring = &adev->jpeg.inst[i].ring_dec[j];
309 				ring->wptr = 0;
310 				ring->wptr_old = 0;
311 				jpeg_v4_0_3_dec_ring_set_wptr(ring);
312 				ring->sched.ready = true;
319 			ring = adev->jpeg.inst[i].ring_dec;
321 			if (ring->use_doorbell)
323 					adev, ring->use_doorbell,
329 				ring = &adev->jpeg.inst[i].ring_dec[j];
330 				if (ring->use_doorbell)
334 						(ring->pipe ? (ring->pipe - 0x15) : 0),
335 						ring->doorbell_index
338 				r = amdgpu_ring_test_helper(ring);
354  * Stop the JPEG block, mark ring as not ready any more
472 	struct amdgpu_ring *ring;
507 			ring = &adev->jpeg.inst[i].ring_dec[j];
525 				reg_offset, lower_32_bits(ring->gpu_addr));
529 				reg_offset, upper_32_bits(ring->gpu_addr));
541 					    reg_offset, ring->ring_size / 4);
542 			ring->wptr = RREG32_SOC15_OFFSET(
592  * @ring: amdgpu_ring pointer
596 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring)
598 	struct amdgpu_device *adev = ring->adev;
601 		JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,
602 		ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
608  * @ring: amdgpu_ring pointer
612 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring)
614 	struct amdgpu_device *adev = ring->adev;
616 	if (ring->use_doorbell)
617 		return adev->wb.wb[ring->wptr_offs];
620 			JPEG, GET_INST(JPEG, ring->me),
622 			ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
628  * @ring: amdgpu_ring pointer
632 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)
634 	struct amdgpu_device *adev = ring->adev;
636 	if (ring->use_doorbell) {
637 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
638 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
640 		WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),
642 				    (ring->pipe ? (0x40 * ring->pipe - 0xc80) :
644 				    lower_32_bits(ring->wptr));
651  * @ring: amdgpu_ring pointer
653  * Write a start command to the ring.
655 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
657 	if (!amdgpu_sriov_vf(ring->adev)) {
658 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
660 		amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
663 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
665 	amdgpu_ring_write(ring, 0x80004000);
671  * @ring: amdgpu_ring pointer
673  * Write a end command to the ring.
675 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)
677 	if (!amdgpu_sriov_vf(ring->adev)) {
678 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
680 		amdgpu_ring_write(ring, 0x62a04);
683 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
685 	amdgpu_ring_write(ring, 0x00004000);
691  * @ring: amdgpu_ring pointer
696  * Write a fence and a trap command to the ring.
698 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
703 	amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
705 	amdgpu_ring_write(ring, seq);
707 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
709 	amdgpu_ring_write(ring, seq);
711 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
713 	amdgpu_ring_write(ring, lower_32_bits(addr));
715 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
717 	amdgpu_ring_write(ring, upper_32_bits(addr));
719 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
721 	amdgpu_ring_write(ring, 0x8);
723 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
725 	amdgpu_ring_write(ring, 0);
727 	if (ring->adev->jpeg.inst[ring->me].aid_id) {
728 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
730 		amdgpu_ring_write(ring, 0x4);
732 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
733 		amdgpu_ring_write(ring, 0);
736 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
738 	amdgpu_ring_write(ring, 0x3fbc);
740 	if (ring->adev->jpeg.inst[ring->me].aid_id) {
741 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
743 		amdgpu_ring_write(ring, 0x0);
745 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
746 		amdgpu_ring_write(ring, 0);
749 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
751 	amdgpu_ring_write(ring, 0x1);
753 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
754 	amdgpu_ring_write(ring, 0);
760  * @ring: amdgpu_ring pointer
765  * Write ring commands to execute the indirect buffer.
767 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
774 	amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
776 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
778 	amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
780 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
782 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
784 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
786 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
788 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
790 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
792 	amdgpu_ring_write(ring, ib->length_dw);
794 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
796 	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
798 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
800 	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
802 	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
803 	amdgpu_ring_write(ring, 0);
805 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
807 	amdgpu_ring_write(ring, 0x01400200);
809 	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
811 	amdgpu_ring_write(ring, 0x2);
813 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET,
815 	amdgpu_ring_write(ring, 0x2);
818 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
823 	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
825 	amdgpu_ring_write(ring, 0x01400200);
827 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
829 	amdgpu_ring_write(ring, val);
831 	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
834 		amdgpu_ring_write(ring, 0);
835 		amdgpu_ring_write(ring,
838 		amdgpu_ring_write(ring, reg_offset);
839 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
842 	amdgpu_ring_write(ring, mask);
845 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
848 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
851 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
857 	jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask);
860 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
864 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
867 		amdgpu_ring_write(ring, 0);
868 		amdgpu_ring_write(ring,
871 		amdgpu_ring_write(ring, reg_offset);
872 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
875 	amdgpu_ring_write(ring, val);
878 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
882 	WARN_ON(ring->wptr % 2 || count % 2);
885 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
886 		amdgpu_ring_write(ring, 0);

Indexes created Sat May 25 20:21:57 MDT 2024