amd/amdgpu/jpeg_v1_0.c

36 static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
38 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
40 	struct amdgpu_device *adev = ring->adev;
41 	ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
44 		ring->ring[(*ptr)++] = 0;
45 		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
47 		ring->ring[(*ptr)++] = reg_offset;
48 		ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
50 	ring->ring[(*ptr)++] = val;
53 static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
55 	struct amdgpu_device *adev = ring->adev;
62 	val = lower_32_bits(ring->gpu_addr);
63 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
68 	val = upper_32_bits(ring->gpu_addr);
69 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
73 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
74 		ring->ring[ptr++] = 0;
81 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
87 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
95 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
96 	ring->ring[ptr++] = 0x01400200;
97 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
98 	ring->ring[ptr++] = val;
99 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
102 		ring->ring[ptr++] = 0;
103 		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
105 		ring->ring[ptr++] = reg_offset;
106 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
108 	ring->ring[ptr++] = mask;
112 		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
113 		ring->ring[ptr++] = 0;
120 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
126 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
132  * @ring: amdgpu_ring pointer
136 static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring)
138 	struct amdgpu_device *adev = ring->adev;
146  * @ring: amdgpu_ring pointer
150 static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring)
152 	struct amdgpu_device *adev = ring->adev;
160  * @ring: amdgpu_ring pointer
164 static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring)
166 	struct amdgpu_device *adev = ring->adev;
168 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
174  * @ring: amdgpu_ring pointer
176  * Write a start command to the ring.
178 static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring)
180 	struct amdgpu_device *adev = ring->adev;
182 	amdgpu_ring_write(ring,
184 	amdgpu_ring_write(ring, 0x68e04);
186 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
187 	amdgpu_ring_write(ring, 0x80010000);
193  * @ring: amdgpu_ring pointer
195  * Write a end command to the ring.
197 static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring)
199 	struct amdgpu_device *adev = ring->adev;
201 	amdgpu_ring_write(ring,
203 	amdgpu_ring_write(ring, 0x68e04);
205 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
206 	amdgpu_ring_write(ring, 0x00010000);
212  * @ring: amdgpu_ring pointer
217  * Write a fence and a trap command to the ring.
219 static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
222 	struct amdgpu_device *adev = ring->adev;
226 	amdgpu_ring_write(ring,
228 	amdgpu_ring_write(ring, seq);
230 	amdgpu_ring_write(ring,
232 	amdgpu_ring_write(ring, seq);
234 	amdgpu_ring_write(ring,
236 	amdgpu_ring_write(ring, lower_32_bits(addr));
238 	amdgpu_ring_write(ring,
240 	amdgpu_ring_write(ring, upper_32_bits(addr));
242 	amdgpu_ring_write(ring,
244 	amdgpu_ring_write(ring, 0x8);
246 	amdgpu_ring_write(ring,
248 	amdgpu_ring_write(ring, 0);
250 	amdgpu_ring_write(ring,
252 	amdgpu_ring_write(ring, 0x01400200);
254 	amdgpu_ring_write(ring,
256 	amdgpu_ring_write(ring, seq);
258 	amdgpu_ring_write(ring,
260 	amdgpu_ring_write(ring, lower_32_bits(addr));
262 	amdgpu_ring_write(ring,
264 	amdgpu_ring_write(ring, upper_32_bits(addr));
266 	amdgpu_ring_write(ring,
268 	amdgpu_ring_write(ring, 0xffffffff);
270 	amdgpu_ring_write(ring,
272 	amdgpu_ring_write(ring, 0x3fbc);
274 	amdgpu_ring_write(ring,
276 	amdgpu_ring_write(ring, 0x1);
279 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
280 	amdgpu_ring_write(ring, 0);
286  * @ring: amdgpu_ring pointer
291  * Write ring commands to execute the indirect buffer.
293 static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,
298 	struct amdgpu_device *adev = ring->adev;
301 	amdgpu_ring_write(ring,
303 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
305 	amdgpu_ring_write(ring,
307 	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
309 	amdgpu_ring_write(ring,
311 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
313 	amdgpu_ring_write(ring,
315 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
317 	amdgpu_ring_write(ring,
319 	amdgpu_ring_write(ring, ib->length_dw);
321 	amdgpu_ring_write(ring,
323 	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
325 	amdgpu_ring_write(ring,
327 	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
329 	amdgpu_ring_write(ring,
331 	amdgpu_ring_write(ring, 0);
333 	amdgpu_ring_write(ring,
335 	amdgpu_ring_write(ring, 0x01400200);
337 	amdgpu_ring_write(ring,
339 	amdgpu_ring_write(ring, 0x2);
341 	amdgpu_ring_write(ring,
343 	amdgpu_ring_write(ring, 0x2);
346 static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring,
350 	struct amdgpu_device *adev = ring->adev;
353 	amdgpu_ring_write(ring,
355 	amdgpu_ring_write(ring, 0x01400200);
357 	amdgpu_ring_write(ring,
359 	amdgpu_ring_write(ring, val);
361 	amdgpu_ring_write(ring,
365 		amdgpu_ring_write(ring, 0);
366 		amdgpu_ring_write(ring,
369 		amdgpu_ring_write(ring, reg_offset);
370 		amdgpu_ring_write(ring,
373 	amdgpu_ring_write(ring, mask);
376 static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring,
379 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
382 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
388 	jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
391 static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring,
394 	struct amdgpu_device *adev = ring->adev;
397 	amdgpu_ring_write(ring,
401 		amdgpu_ring_write(ring, 0);
402 		amdgpu_ring_write(ring,
405 		amdgpu_ring_write(ring, reg_offset);
406 		amdgpu_ring_write(ring,
409 	amdgpu_ring_write(ring, val);
412 static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)
416 	WARN_ON(ring->wptr % 2 || count % 2);
419 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
420 		amdgpu_ring_write(ring, 0);
456  * Set ring and irq function pointers
480 	struct amdgpu_ring *ring;
488 	ring = adev->jpeg.inst->ring_dec;
489 	ring->vm_hub = AMDGPU_MMHUB0(0);
490 	sprintf(ring->name, "jpeg_dec");
491 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
526 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
532 		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
533 		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
540 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
542 	/* copy patch commands to the jpeg ring */
543 	jpeg_v1_0_decode_ring_set_patch_ring(ring,
544 		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
597 static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
599 	struct	amdgpu_device *adev = ring->adev;
606 		DRM_ERROR("JPEG dec: vcn dec ring may not be empty\n");
610 			DRM_ERROR("JPEG dec: vcn enc ring[%d] may not be empty\n", cnt);
613 	vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);