amd/amdgpu/ih_v6_1.c

40  * ih_v6_1_init_register_offset - Initialize register offset for ih rings
44  * Initialize register offset ih rings (IH_V6_0).
50 	/* ih ring 2 is removed
51 	 * ih ring and ih ring 1 are available */
52 	if (adev->irq.ih.ring_size) {
53 		ih_regs = &adev->irq.ih.ih_regs;
122  * @ih: amdgpu_ih_ring pointer
128 					  struct amdgpu_ih_ring *ih,
134 	ih_regs = &ih->ih_regs;
139 	if (ih == &adev->irq.ih)
150 		ih->enabled = true;
155 		ih->enabled = false;
156 		ih->rptr = 0;
172 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
176 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
177 		if (ih[i]->ring_size) {
178 			r = ih_v6_1_toggle_ring_interrupts(adev, ih[i], enable);
187 static uint32_t ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
189 	int rb_bufsz = order_base_2(ih->ring_size / 4);
192 				   MC_SPACE, ih->use_bus_addr ? 2 : 4);
210 static uint32_t ih_v6_1_doorbell_rptr(struct amdgpu_ih_ring *ih)
214 	if (ih->use_doorbell) {
217 						 ih->doorbell_index);
230  * ih_v6_1_enable_ring - enable an ih ring buffer
233  * @ih: amdgpu_ih_ring pointer
235  * Enable an ih ring buffer (IH_V6_0)
238 				      struct amdgpu_ih_ring *ih)
243 	ih_regs = &ih->ih_regs;
246 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
247 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
250 	tmp = ih_v6_1_rb_cntl(ih, tmp);
251 	if (ih == &adev->irq.ih)
253 	if (ih == &adev->irq.ih1) {
267 	if (ih == &adev->irq.ih) {
268 		/* set the ih ring 0 writeback address whether it's enabled or not */
269 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
270 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
277 	WREG32(ih_regs->ih_doorbell_rptr, ih_v6_1_doorbell_rptr(ih));
295 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
310 		if (ih[0]->use_bus_addr) {
318 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
319 		if (ih[i]->ring_size) {
320 			ret = ih_v6_1_enable_ring(adev, ih[i]);
326 	/* update doorbell range for ih ring 0 */
327 	adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
328 					    ih[0]->doorbell_index);
384  * @ih: amdgpu_ih_ring pointer
392 			      struct amdgpu_ih_ring *ih)
397 	wptr = le32_to_cpu(*ih->wptr_cpu);
398 	ih_regs = &ih->ih_regs;
412 	tmp = (wptr + 32) & ih->ptr_mask;
415 		 wptr, ih->rptr, tmp);
416 	ih->rptr = tmp;
429 	return (wptr & ih->ptr_mask);
436  * @ih: amdgpu_ih_ring pointer
440 			       struct amdgpu_ih_ring *ih)
446 	ih_regs = &ih->ih_regs;
451 		if ((v < ih->ring_size) && (v != ih->rptr))
452 			WDOORBELL32(ih->doorbell_index, ih->rptr);
462  * @ih: amdgpu_ih_ring pointer
467 			       struct amdgpu_ih_ring *ih)
471 	if (ih->use_doorbell) {
473 		*ih->rptr_cpu = ih->rptr;
474 		WDOORBELL32(ih->doorbell_index, ih->rptr);
477 			ih_v6_1_irq_rearm(adev, ih);
479 		ih_regs = &ih->ih_regs;
480 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
541 	/* use gpu virtual address for ih ring
543 	 * use bus address for ih ring by psp bl */
546 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
550 	adev->irq.ih.use_doorbell = true;
551 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
556 	/* initialize ih control register offset */
670 	/* Disable ih sram power cntl before switch powergating mode */