Lines Matching defs:vmid
161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
163 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
221 uint8_t vmid, uint16_t *p_pasid)
226 + vmid);
243 * @vmid: vm instance to flush
249 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
254 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
275 1 << vmid, GET_INST(GC, 0));
317 tmp &= 1 << vmid;
351 int vmid, i;
353 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
356 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
364 gmc_v10_0_flush_gpu_tlb(adev, vmid, i,
367 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
374 unsigned int vmid, uint64_t pd_addr)
378 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
396 (hub->ctx_addr_distance * vmid),
400 (hub->ctx_addr_distance * vmid),
407 req, 1 << vmid);
421 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
432 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
434 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;