amd/amdgpu/gfxhub_v3_0_3.c

191 	uint32_t tmp;
194 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
196 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
197 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
198 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
200 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
202 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
203 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
206 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
211 	uint32_t tmp;
220 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
221 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
222 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
223 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
226 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
228 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
229 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
230 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
231 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
233 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
234 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
235 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
236 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
238 	tmp = regGCVM_L2_CNTL3_DEFAULT;
240 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
241 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
244 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
245 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
248 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
250 	tmp = regGCVM_L2_CNTL4_DEFAULT;
251 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
252 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
253 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
255 	tmp = regGCVM_L2_CNTL5_DEFAULT;
256 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
257 	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
262 	uint32_t tmp;
264 	tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
265 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
266 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
267 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
269 	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
299 	uint32_t tmp;
302 		tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
303 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
304 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
306 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
308 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
310 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
312 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
314 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
316 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
318 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
320 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
324 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
328 				    i * hub->ctx_distance, tmp);
341 	hub->vm_cntx_cntl = tmp;
376 	u32 tmp;
385 	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
386 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
387 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
389 	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
405 	u32 tmp;
413 	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
414 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
416 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
418 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
420 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
422 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
425 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
427 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
429 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
431 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
433 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
435 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
438 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
440 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
443 	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);