amd/amdgpu/gfx_v9_0.c

766 					      unsigned int vmid);
794 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
795 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
824 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
856 	/* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2289 	/* Calculate trap config vmid mask */
2345 	int vmid;
2353 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
2354 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
2355 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
2356 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
2357 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
3103 	/* set the RB to use vmid 0 */
3311 	/* set MQD vmid to 0 */
3351 	/* set the vmid for the queue */
3422 	/* set MQD vmid to 0 */
3474 	/* set the vmid for the queue */
4033 					  uint32_t vmid,
4042 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
4047 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
4052 				   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
4057 				   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
4885 					      unsigned int vmid)
4896 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4904 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
4908 	gfx_v9_0_update_spm_vmid_internal(adev, vmid);
5142 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5150 	control |= ib->length_dw | (vmid << 24);
5158 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
5259 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5260 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5342 					unsigned vmid, uint64_t pd_addr)
5344 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5691 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
5699 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);