amd/amdgpu/gfx_v8_0.c

2078 	u32 reg_offset;
2083 	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2084 		modearray[reg_offset] = 0;
2086 	for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)
2087 		mod2array[reg_offset] = 0;
2251 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2252 			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2253 			    reg_offset != 23)
2254 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2256 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2257 			if (reg_offset != 7)
2258 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2443 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2444 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2446 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2447 			if (reg_offset != 7)
2448 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2632 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2633 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2635 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2636 			if (reg_offset != 7)
2637 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2835 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2836 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2838 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2839 			if (reg_offset != 7)
2840 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3037 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3038 			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3040 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3041 			if (reg_offset != 7)
3042 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3206 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3207 			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3208 			    reg_offset != 23)
3209 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3211 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3212 			if (reg_offset != 7)
3213 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3383 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3384 			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3385 			    reg_offset != 23)
3386 				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3388 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3389 			if (reg_offset != 7)
3390 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);