amd/amdgpu/gfx_v11_0.c

152 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
153 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
189 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
192 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
930 				   int me, int pipe, int queue)
940 	ring->queue = queue;
950 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
961 				       int mec, int pipe, int queue)
973 	ring->queue = queue;
981 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3594 	/* tell RLC which is KIQ queue */
3597 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3646 	/* set up default queue priority level
3698 	/* active the queue */
3713 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3807 	/* disable the queue if it's active */
3871 	/* set the vmid for the queue */
3883 	/* set static priority for a compute queue/ring */
3898 	/* inactivate the queue */
3919 	/* disable the queue if it's active */
3986 	/* set the vmid for the queue */
3992 	/* activate the queue */
4019 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4028 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4050 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5948 		struct amdgpu_mes_queue *queue;
5953 		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5954 		if (queue) {
5955 			DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5956 			amdgpu_fence_process(queue->ring);
5975 				/* Per-queue interrupt is supported for MEC starting from VI.
5977 				 * of per queue.
5981 				    (ring->queue == queue_id))
6044 			/* we only enabled 1 gfx queue per pipe for now */
6054 			    ring->queue == queue_id)