amd/amdgpu/gfx_v11_0.c

786 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
789 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
794 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
799 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
807 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
814 	/* type 3 wave data */
816 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
817 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
818 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
819 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
820 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
821 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
822 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
823 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
824 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
825 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
826 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
827 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
828 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
829 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
830 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
834 				     uint32_t wave, uint32_t start,
840 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
845 				      uint32_t wave, uint32_t thread,
850 		adev, wave, thread,
5363 	/* Currently, there is a high possibility to get wave ID mismatch
5365 	 * different wave IDs than the GDS expects. This situation happens
5367 	 * The wave IDs generated by ME are also wrong after suspend/resume.
5370 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and