amd/amdgpu/gfx_v11_0.c

395 		uint32_t padding, offset;
397 		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
401 		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
402 		ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
999 	unsigned int		offset;
1010 		rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
1027 	/* In case the offset in rlc toc ucode is aligned */
1028 	if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
1029 		total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
1070 	toc_offset = rlc_autoload_info[id].offset;
1310 	rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
2619 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2621 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2626 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2628 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2633 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2635 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2641 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2646 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2651 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
5678 	uint64_t offset, gds_addr, de_payload_gpu_addr;
5683 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5687 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5689 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5691 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5694 		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5696 		offset = offsetof(struct v10_gfx_meta_data, de_payload);
5697 		de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5698 		de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;