Lines Matching refs:vmid

3592 					       unsigned int vmid);
3631 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3632 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3663 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3694 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4939 /* Calculate trap config vmid mask */
4994 int vmid;
5002 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5003 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5004 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5005 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5006 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
6218 /* set the RB to use vmid 0 */
6498 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6687 /* set MQD vmid to 0 */
6727 /* set the vmid for the queue */
6798 /* set MQD vmid to 0 */
6841 /* set the vmid for the queue */
7520 uint32_t vmid,
7529 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7534 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7539 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7544 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
8053 unsigned int vmid)
8061 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8066 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8070 gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8448 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8456 control |= ib->length_dw | (vmid << 24);
8464 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8470 /* inherit vmid from mqd */
8489 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8490 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8493 /* inherit vmid from mqd */
8580 unsigned int vmid, uint64_t pd_addr)
8585 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8891 unsigned int vmid)
8899 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);