Lines Matching refs:tmp
3873 uint32_t tmp = 0;
3892 tmp = RREG32(scratch);
3893 if (tmp == 0xDEADBEEF)
5015 u32 tmp, wgp_active_bitmap = 0;
5060 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5062 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5063 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5064 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5066 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5068 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5069 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5070 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5098 u32 tmp;
5118 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5120 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5122 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5137 u32 tmp;
5142 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5144 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5146 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5148 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5150 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5153 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5179 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5181 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5182 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5230 uint32_t tmp;
5233 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5234 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5235 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5236 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5559 uint32_t rlc_g_offset, rlc_g_size, tmp;
5574 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5575 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5581 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5582 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5593 uint32_t tmp;
5598 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5599 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5600 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5604 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5605 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5630 uint32_t tmp;
5635 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5636 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5637 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5641 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5642 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5667 uint32_t tmp;
5672 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5673 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5674 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5678 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5679 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5704 uint32_t tmp;
5709 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5710 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5711 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5715 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5716 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5784 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5786 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5787 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5788 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5791 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5793 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5816 uint32_t tmp;
5845 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5846 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5847 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5851 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5852 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5866 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5867 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5868 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5869 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5870 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5871 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5894 uint32_t tmp;
5923 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5924 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5925 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5929 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5930 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5944 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5945 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5946 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5947 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5948 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5971 uint32_t tmp;
6000 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6001 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6002 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6006 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6007 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6021 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6022 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6023 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6024 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6025 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6155 u32 tmp;
6157 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6158 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6160 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6166 u32 tmp;
6169 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6171 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6173 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6176 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6179 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6190 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6192 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6198 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6200 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6211 u32 tmp;
6228 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6229 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6231 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6233 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6253 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6271 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6272 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6273 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6290 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6359 u32 tmp;
6375 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6376 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6377 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6381 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6382 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6396 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6397 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6398 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6399 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6400 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6426 uint32_t tmp;
6439 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6440 tmp &= 0xffffff00;
6441 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6442 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6443 tmp |= 0x80;
6444 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6447 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6448 tmp &= 0xffffff00;
6449 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6450 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6451 tmp |= 0x80;
6452 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6462 u32 tmp;
6470 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6471 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6472 mqd->cp_gfx_hqd_queue_priority = tmp;
6480 uint32_t tmp;
6492 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6493 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6494 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6495 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6496 mqd->cp_gfx_mqd_control = tmp;
6499 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6500 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6507 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6508 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6509 mqd->cp_gfx_hqd_quantum = tmp;
6529 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6530 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6531 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6533 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6535 mqd->cp_gfx_hqd_cntl = tmp;
6538 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6540 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6542 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6545 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6547 mqd->cp_rb_doorbell_control = tmp;
6637 uint32_t tmp;
6652 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6653 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6656 mqd->cp_hqd_eop_control = tmp;
6659 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6668 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6675 mqd->cp_hqd_pq_doorbell_control = tmp;
6688 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6689 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6690 mqd->cp_mqd_control = tmp;
6698 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6699 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6701 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6706 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6707 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6709 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6710 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6711 mqd->cp_hqd_pq_control = tmp;
6730 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6731 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6732 mqd->cp_hqd_persistent_state = tmp;
6735 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6736 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6737 mqd->cp_hqd_ib_control = tmp;
7350 u32 tmp;
7355 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7358 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7368 u32 tmp;
7372 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7373 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7386 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7393 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7402 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7409 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7428 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7429 tmp |= grbm_soft_reset;
7430 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7431 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7432 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7436 tmp &= ~grbm_soft_reset;
7437 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7438 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
9190 uint32_t tmp, target;
9202 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9203 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9205 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9207 tmp = RREG32_SOC15_IP(GC, target);
9208 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9210 WREG32_SOC15_IP(GC, target, tmp);
9212 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9213 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9215 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9217 tmp = RREG32_SOC15_IP(GC, target);
9218 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9220 WREG32_SOC15_IP(GC, target, tmp);