Lines Matching refs:tmp
216 u32 tmp;
227 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
228 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
231 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
234 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
265 u32 tmp;
268 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
269 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
270 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
278 u32 tmp;
281 tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
282 tmp &=
285 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
286 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
288 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
290 return tmp;
307 u32 tmp;
314 tmp = RREG32_SOC15(DF, 0,
316 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
317 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
319 mmDF_PIE_AON0_DfGlobalClkGater, tmp);
321 tmp = RREG32_SOC15(DF, 0,
323 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
324 tmp |= DF_V3_6_MGCG_DISABLE;
326 mmDF_PIE_AON0_DfGlobalClkGater, tmp);
337 u32 tmp;
340 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
341 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)