Lines Matching refs:tmp
46 u32 tmp;
49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
50 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
51 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
59 u32 tmp;
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
62 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
63 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
65 return tmp;
80 u32 tmp;
86 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
87 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
88 tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
89 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
91 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
92 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
93 tmp |= DF_V1_7_MGCG_DISABLE;
94 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
104 u32 tmp;
107 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
108 if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)