amd/amdgpu/dce_v8_0.c

192 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
195 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
198 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
201 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
204 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
532 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
583 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
1078 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1082 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1083 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1087 	tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1090 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1091 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1095 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1787 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1789 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1951 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1953 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1955 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1957 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1959 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1961 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1962 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1969 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1976 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1977 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1978 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1979 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1980 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1981 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1984 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1988 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1993 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1997 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2001 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2026 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2029 		WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2042 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2045 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2047 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2049 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2053 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2055 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2056 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2057 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2059 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2060 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2061 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2063 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2064 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2066 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2071 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2077 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2081 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2084 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2087 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2091 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2095 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2206 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2211 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2219 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2229 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2231 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2234 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2264 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2265 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2266 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2634 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];