amd/amdgpu/dce_v8_0.c

667  * @wm: watermark calculation data
673 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
681 	yclk.full = dfixed_const(wm->yclk);
683 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
696  * @wm: watermark calculation data
702 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
710 	yclk.full = dfixed_const(wm->yclk);
712 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
725  * @wm: watermark calculation data
731 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
739 	sclk.full = dfixed_const(wm->sclk);
754  * @wm: watermark calculation data
760 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
768 	disp_clk.full = dfixed_const(wm->disp_clk);
785  * @wm: watermark calculation data
791 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
794 	u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
795 	u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
796 	u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
804  * @wm: watermark calculation data
810 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
823 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
825 	bpp.full = dfixed_const(wm->bytes_per_pixel);
826 	src_width.full = dfixed_const(wm->src_width);
828 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
837  * @wm: watermark calculation data
843 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
847 	u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
850 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
851 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
852 		(wm->num_heads * cursor_line_pair_return_time);
858 	if (wm->num_heads == 0)
863 	if ((wm->vsc.full > a.full) ||
864 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
865 	    (wm->vtaps >= 5) ||
866 	    ((wm->vsc.full >= a.full) && wm->interlaced))
872 	b.full = dfixed_const(wm->num_heads);
874 	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
877 	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
879 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
886 	if (line_fill_time < wm->active_time)
889 		return latency + (line_fill_time - wm->active_time);
897  * @wm: watermark calculation data
904 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
906 	if (dce_v8_0_average_bandwidth(wm) <=
907 	    (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
917  * @wm: watermark calculation data
924 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
926 	if (dce_v8_0_average_bandwidth(wm) <=
927 	    (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
936  * @wm: watermark calculation data
942 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
944 	u32 lb_partitions = wm->lb_size / wm->src_width;
945 	u32 line_time = wm->active_time + wm->blank_time;
951 	if (wm->vsc.full > a.full)
954 		if (lb_partitions <= (wm->vtaps + 1))
960 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
962 	if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1077 	/* select wm A */
1086 	/* select wm B */