amd/amdgpu/dce_v8_0.c

89 	uint32_t	hpd;
95 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
220  * dce_v8_0_hpd_sense - hpd sense callback.
223  * @hpd: hpd (hotplug detect) pin
229 			       enum amdgpu_hpd_id hpd)
233 	if (hpd >= adev->mode_info.num_hpd)
236 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
244  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
247  * @hpd: hpd (hotplug detect) pin
249  * Set the polarity of the hpd pin (evergreen+).
252 				      enum amdgpu_hpd_id hpd)
255 	bool connected = dce_v8_0_hpd_sense(adev, hpd);
257 	if (hpd >= adev->mode_info.num_hpd)
260 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
265 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
269 				 int hpd)
273 	if (hpd >= adev->mode_info.num_hpd) {
274 		DRM_DEBUG("invalid hdp %d\n", hpd);
278 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
280 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
284  * dce_v8_0_hpd_init - hpd setup callback.
288  * Setup the hpd pins used by the card (evergreen+).
289  * Enable the pin, set the polarity, and enable the hpd interrupts.
302 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
305 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
307 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
311 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
316 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
318 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
322 		dce_v8_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
323 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
324 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
330  * dce_v8_0_hpd_fini - hpd tear down callback.
334  * Tear down the hpd pins used by the card (evergreen+).
335  * Disable the hpd interrupts.
348 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
351 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
353 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
355 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
2794 	/* initialize hpd */
3197 	unsigned hpd;
3204 	hpd = entry->src_data[0];
3205 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3206 	mask = interrupt_status_offsets[hpd].hpd;
3209 		dce_v8_0_hpd_int_ack(adev, hpd);
3211 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);