amd/amdgpu/dce_v6_0.c

94 	uint32_t	hpd;
100 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
229  * dce_v6_0_hpd_sense - hpd sense callback.
232  * @hpd: hpd (hotplug detect) pin
238 			       enum amdgpu_hpd_id hpd)
242 	if (hpd >= adev->mode_info.num_hpd)
245 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
252  * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
255  * @hpd: hpd (hotplug detect) pin
257  * Set the polarity of the hpd pin (evergreen+).
260 				      enum amdgpu_hpd_id hpd)
263 	bool connected = dce_v6_0_hpd_sense(adev, hpd);
265 	if (hpd >= adev->mode_info.num_hpd)
268 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
273 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
277 				 int hpd)
281 	if (hpd >= adev->mode_info.num_hpd) {
282 		DRM_DEBUG("invalid hdp %d\n", hpd);
286 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
288 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
292  * dce_v6_0_hpd_init - hpd setup callback.
296  * Setup the hpd pins used by the card (evergreen+).
297  * Enable the pin, set the polarity, and enable the hpd interrupts.
310 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
313 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
315 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
319 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
324 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
326 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
330 		dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
331 		dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
332 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
338  * dce_v6_0_hpd_fini - hpd tear down callback.
342  * Tear down the hpd pins used by the card (evergreen+).
343  * Disable the hpd interrupts.
356 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
359 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
361 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
363 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
2772 	/* initialize hpd */
3109 	unsigned hpd;
3116 	hpd = entry->src_data[0];
3117 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3118 	mask = interrupt_status_offsets[hpd].hpd;
3121 		dce_v6_0_hpd_int_ack(adev, hpd);
3123 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);