Lines Matching refs:amdgpu_crtc
261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
262 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
609 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
618 * @amdgpu_crtc: the selected display controller
627 struct amdgpu_crtc *amdgpu_crtc,
631 u32 pipe_offset = amdgpu_crtc->crtc_id;
640 if (amdgpu_crtc->base.enabled && mode) {
660 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
662 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
675 if (amdgpu_crtc->base.enabled && mode) {
1051 * @amdgpu_crtc: the selected display controller
1059 struct amdgpu_crtc *amdgpu_crtc,
1062 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1069 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1094 wm_high.vsc = amdgpu_crtc->vsc;
1096 if (amdgpu_crtc->rmx_type != RMX_OFF)
1133 wm_low.vsc = amdgpu_crtc->vsc;
1135 if (amdgpu_crtc->rmx_type != RMX_OFF)
1157 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1159 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1160 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1163 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1167 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1170 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1172 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1175 amdgpu_crtc->line_time = line_time;
1176 amdgpu_crtc->wm_high = latency_watermark_a;
1177 amdgpu_crtc->wm_low = latency_watermark_b;
1179 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1592 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1607 amdgpu_crtc->crtc_id);
1639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1640 bpc = amdgpu_crtc->bpc;
1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1876 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1880 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1885 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1892 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1899 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2068 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2071 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2073 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2075 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2077 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2079 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2081 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2082 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2089 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2094 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2099 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2100 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2101 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2102 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2103 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2104 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2107 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2111 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2116 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2120 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2124 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2146 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2149 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2154 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2159 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2166 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2168 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2170 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2172 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2174 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2176 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2178 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2180 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2182 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2183 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2184 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2186 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2187 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2188 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2190 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2191 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2193 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2198 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2204 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2208 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2210 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2212 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2214 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2216 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2218 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2220 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2223 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2227 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2229 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2296 to_amdgpu_encoder(amdgpu_crtc->encoder);
2299 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2324 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2366 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2369 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2374 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2379 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2383 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2385 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2390 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2394 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2395 upper_32_bits(amdgpu_crtc->cursor_addr));
2396 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2397 lower_32_bits(amdgpu_crtc->cursor_addr));
2399 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2402 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2408 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2412 amdgpu_crtc->cursor_x = x;
2413 amdgpu_crtc->cursor_y = y;
2421 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2425 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2429 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2430 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2431 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2432 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2457 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2469 if ((width > amdgpu_crtc->max_cursor_width) ||
2470 (height > amdgpu_crtc->max_cursor_height)) {
2477 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2495 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2499 if (width != amdgpu_crtc->cursor_width ||
2500 height != amdgpu_crtc->cursor_height ||
2501 hot_x != amdgpu_crtc->cursor_hot_x ||
2502 hot_y != amdgpu_crtc->cursor_hot_y) {
2505 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2506 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2510 amdgpu_crtc->cursor_width = width;
2511 amdgpu_crtc->cursor_height = height;
2512 amdgpu_crtc->cursor_hot_x = hot_x;
2513 amdgpu_crtc->cursor_hot_y = hot_y;
2520 if (amdgpu_crtc->cursor_bo) {
2521 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2527 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2530 amdgpu_crtc->cursor_bo = obj;
2536 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2538 if (amdgpu_crtc->cursor_bo) {
2541 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2542 amdgpu_crtc->cursor_y);
2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2564 kfree(amdgpu_crtc);
2584 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2589 amdgpu_crtc->enabled = true;
2596 amdgpu_crtc->crtc_id);
2606 if (amdgpu_crtc->enabled) {
2612 amdgpu_crtc->enabled = false;
2635 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663 i != amdgpu_crtc->crtc_id &&
2664 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2672 switch (amdgpu_crtc->pll_id) {
2677 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2687 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2694 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2695 amdgpu_crtc->adjusted_clock = 0;
2696 amdgpu_crtc->encoder = NULL;
2697 amdgpu_crtc->connector = NULL;
2705 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2709 if (!amdgpu_crtc->adjusted_clock)
2717 to_amdgpu_encoder(amdgpu_crtc->encoder);
2719 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2722 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2723 amdgpu_crtc->pll_id,
2726 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2736 amdgpu_crtc->hw_mode = *adjusted_mode;
2745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2752 amdgpu_crtc->encoder = encoder;
2753 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2757 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2758 amdgpu_crtc->encoder = NULL;
2759 amdgpu_crtc->connector = NULL;
2767 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2769 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2770 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2803 struct amdgpu_crtc *amdgpu_crtc;
2805 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2807 if (amdgpu_crtc == NULL)
2810 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2812 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2813 amdgpu_crtc->crtc_id = index;
2814 adev->mode_info.crtcs[index] = amdgpu_crtc;
2816 amdgpu_crtc->max_cursor_width = 128;
2817 amdgpu_crtc->max_cursor_height = 128;
2818 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2819 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2821 switch (amdgpu_crtc->crtc_id) {
2824 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2827 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2830 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2833 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2836 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2839 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2843 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2844 amdgpu_crtc->adjusted_clock = 0;
2845 amdgpu_crtc->encoder = NULL;
2846 amdgpu_crtc->connector = NULL;
2847 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
3284 struct amdgpu_crtc *amdgpu_crtc;
3288 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3301 if(amdgpu_crtc == NULL)
3305 works = amdgpu_crtc->pflip_works;
3306 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3307 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3309 amdgpu_crtc->pflip_status,
3316 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3317 amdgpu_crtc->pflip_works = NULL;
3321 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3325 drm_crtc_vblank_put(&amdgpu_crtc->base);