amd/amdgpu/dce_v11_0.c

746  * @wm: watermark calculation data
752 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
760 	yclk.full = dfixed_const(wm->yclk);
762 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
775  * @wm: watermark calculation data
781 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
789 	yclk.full = dfixed_const(wm->yclk);
791 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
804  * @wm: watermark calculation data
810 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
818 	sclk.full = dfixed_const(wm->sclk);
833  * @wm: watermark calculation data
839 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
847 	disp_clk.full = dfixed_const(wm->disp_clk);
864  * @wm: watermark calculation data
870 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
873 	u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
874 	u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
875 	u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
883  * @wm: watermark calculation data
889 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
902 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
904 	bpp.full = dfixed_const(wm->bytes_per_pixel);
905 	src_width.full = dfixed_const(wm->src_width);
907 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
916  * @wm: watermark calculation data
922 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
926 	u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
929 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
930 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
931 		(wm->num_heads * cursor_line_pair_return_time);
937 	if (wm->num_heads == 0)
942 	if ((wm->vsc.full > a.full) ||
943 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
944 	    (wm->vtaps >= 5) ||
945 	    ((wm->vsc.full >= a.full) && wm->interlaced))
951 	b.full = dfixed_const(wm->num_heads);
953 	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
956 	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
958 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
965 	if (line_fill_time < wm->active_time)
968 		return latency + (line_fill_time - wm->active_time);
976  * @wm: watermark calculation data
983 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
985 	if (dce_v11_0_average_bandwidth(wm) <=
986 	    (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
996  * @wm: watermark calculation data
1003 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1005 	if (dce_v11_0_average_bandwidth(wm) <=
1006 	    (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1015  * @wm: watermark calculation data
1021 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1023 	u32 lb_partitions = wm->lb_size / wm->src_width;
1024 	u32 line_time = wm->active_time + wm->blank_time;
1030 	if (wm->vsc.full > a.full)
1033 		if (lb_partitions <= (wm->vtaps + 1))
1039 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1041 	if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1156 	/* select wm A */
1164 	/* select wm B */