amd/amdgpu/dce_v11_0.c

55 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
94 	uint32_t        hpd;
100 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
296  * dce_v11_0_hpd_sense - hpd sense callback.
299  * @hpd: hpd (hotplug detect) pin
305 			       enum amdgpu_hpd_id hpd)
309 	if (hpd >= adev->mode_info.num_hpd)
312 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
320  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
323  * @hpd: hpd (hotplug detect) pin
325  * Set the polarity of the hpd pin (evergreen+).
328 				      enum amdgpu_hpd_id hpd)
331 	bool connected = dce_v11_0_hpd_sense(adev, hpd);
333 	if (hpd >= adev->mode_info.num_hpd)
336 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
341 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
345  * dce_v11_0_hpd_init - hpd setup callback.
349  * Setup the hpd pins used by the card (evergreen+).
350  * Enable the pin, set the polarity, and enable the hpd interrupts.
363 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
368 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
373 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
375 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
379 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
381 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
383 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
390 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
392 		dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
393 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
394 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
400  * dce_v11_0_hpd_fini - hpd tear down callback.
404  * Tear down the hpd pins used by the card (evergreen+).
405  * Disable the hpd interrupts.
418 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
421 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
423 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
425 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
3014 	/* initialize hpd */
3179 					unsigned hpd,
3184 	if (hpd >= adev->mode_info.num_hpd) {
3185 		DRM_DEBUG("invalid hdp %d\n", hpd);
3191 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3193 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3196 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3198 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3332 				  int hpd)
3336 	if (hpd >= adev->mode_info.num_hpd) {
3337 		DRM_DEBUG("invalid hdp %d\n", hpd);
3341 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3343 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3420 	unsigned hpd;
3427 	hpd = entry->src_data[0];
3428 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3429 	mask = interrupt_status_offsets[hpd].hpd;
3432 		dce_v11_0_hpd_int_ack(adev, hpd);
3434 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);