amd/amdgpu/dce_v10_0.c

55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
90 	uint32_t        hpd;
96 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
272  * dce_v10_0_hpd_sense - hpd sense callback.
275  * @hpd: hpd (hotplug detect) pin
281 			       enum amdgpu_hpd_id hpd)
285 	if (hpd >= adev->mode_info.num_hpd)
288 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
296  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
299  * @hpd: hpd (hotplug detect) pin
301  * Set the polarity of the hpd pin (evergreen+).
304 				      enum amdgpu_hpd_id hpd)
307 	bool connected = dce_v10_0_hpd_sense(adev, hpd);
309 	if (hpd >= adev->mode_info.num_hpd)
312 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
317 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
321  * dce_v10_0_hpd_init - hpd setup callback.
325  * Setup the hpd pins used by the card (evergreen+).
326  * Enable the pin, set the polarity, and enable the hpd interrupts.
339 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
344 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
349 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
351 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
355 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
357 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
359 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
366 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
368 		dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
369 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
371 			       amdgpu_connector->hpd.hpd);
377  * dce_v10_0_hpd_fini - hpd tear down callback.
381  * Tear down the hpd pins used by the card (evergreen+).
382  * Disable the hpd interrupts.
395 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
398 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
400 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
403 			       amdgpu_connector->hpd.hpd);
2876 	/* initialize hpd */
3048 				       unsigned hpd,
3053 	if (hpd >= adev->mode_info.num_hpd) {
3054 		DRM_DEBUG("invalid hdp %d\n", hpd);
3060 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3062 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3065 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3067 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3201 				  int hpd)
3205 	if (hpd >= adev->mode_info.num_hpd) {
3206 		DRM_DEBUG("invalid hdp %d\n", hpd);
3210 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3212 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3288 	unsigned hpd;
3295 	hpd = entry->src_data[0];
3296 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3297 	mask = interrupt_status_offsets[hpd].hpd;
3300 		dce_v10_0_hpd_int_ack(adev, hpd);
3302 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);