Lines Matching refs:ih
69 adev->irq.ih.enabled = true;
91 adev->irq.ih.enabled = false;
92 adev->irq.ih.rptr = 0;
108 struct amdgpu_ih_ring *ih = &adev->irq.ih;
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
182 * @ih: IH ring buffer to fetch wptr
191 struct amdgpu_ih_ring *ih)
195 wptr = le32_to_cpu(*ih->wptr_cpu);
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
214 ih->rptr = (wptr + 16) & ih->ptr_mask;
226 return (wptr & ih->ptr_mask);
233 * @ih: IH ring buffer to decode
240 struct amdgpu_ih_ring *ih,
244 u32 ring_index = ih->rptr >> 2;
247 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
248 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
249 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
250 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
260 ih->rptr += 16;
267 * @ih: IH ring buffer to set rptr
272 struct amdgpu_ih_ring *ih)
274 WREG32(mmIH_RB_RPTR, ih->rptr);
296 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);