Lines Matching defs:ih
69 adev->irq.ih.enabled = true;
91 adev->irq.ih.enabled = false;
92 adev->irq.ih.rptr = 0;
108 struct amdgpu_ih_ring *ih = &adev->irq.ih;
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
180 * @ih: IH ring buffer to fetch wptr
189 struct amdgpu_ih_ring *ih)
193 wptr = le32_to_cpu(*ih->wptr_cpu);
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
203 ih->rptr = (wptr + 16) & ih->ptr_mask;
214 return (wptr & ih->ptr_mask);
249 struct amdgpu_ih_ring *ih,
253 u32 ring_index = ih->rptr >> 2;
256 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
257 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
258 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
259 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
269 ih->rptr += 16;
276 * @ih: IH ring buffer to set wptr
281 struct amdgpu_ih_ring *ih)
283 WREG32(mmIH_RB_RPTR, ih->rptr);
305 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);