amd/amdgpu/atombios_encoders.c

552 	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
598 			args.v1.ucAction = action;
599 			args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
603 				args.v1.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
605 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
606 				args.v1.ucLaneNum = dp_lane_count;
608 				args.v1.ucLaneNum = 8;
610 				args.v1.ucLaneNum = 4;
612 			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
613 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
616 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
620 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
623 				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
627 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
629 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
648 				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
669 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
671 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
673 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
675 					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
740 	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
825 			args.v1.ucAction = action;
827 				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
829 				args.v1.asMode.ucLaneSel = lane_num;
830 				args.v1.asMode.ucLaneSet = lane_set;
833 					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
835 					args.v1.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
837 					args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
840 			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
843 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
845 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
848 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
850 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
853 				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
856 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
858 					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1165 	args.v1.ucAction = action;
1185 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1236 			args.v1.sDigEncoder.ucAction = action;
1237 			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
1238 			args.v1.sDigEncoder.ucEncoderMode =
1241 			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1243 					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1244 				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1246 				args.v1.sDigEncoder.ucLaneNum = 8;
1248 				args.v1.sDigEncoder.ucLaneNum = 4;
1427 	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1454 			args.v1.ucCRTC = amdgpu_crtc->crtc_id;
1458 				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1463 					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1465 					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1470 				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1475 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1477 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1479 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1484 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1486 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1488 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;