amd/amdgpu/atombios_encoders.c

554 	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
601 				args.v3.ucPanelMode = panel_mode;
633 			args.v3.ucAction = action;
634 			args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
636 				args.v3.ucPanelMode = panel_mode;
638 				args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
640 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
641 				args.v3.ucLaneNum = dp_lane_count;
643 				args.v3.ucLaneNum = 8;
645 				args.v3.ucLaneNum = 4;
647 			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
649 			args.v3.acConfig.ucDigSel = dig->dig_encoder;
650 			args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
742 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
904 			args.v3.ucAction = action;
906 				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
908 				args.v3.asMode.ucLaneSel = lane_num;
909 				args.v3.asMode.ucLaneSet = lane_set;
912 					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
914 					args.v3.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);
916 					args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
920 				args.v3.ucLaneNum = dp_lane_count;
922 				args.v3.ucLaneNum = 8;
924 				args.v3.ucLaneNum = 4;
927 				args.v3.acConfig.ucLinkSel = 1;
929 				args.v3.acConfig.ucEncoderSel = 1;
937 				args.v3.acConfig.ucRefClkSource = 2; /* external src */
939 				args.v3.acConfig.ucRefClkSource = pll_id;
943 				args.v3.acConfig.ucTransmitterSel = 0;
946 				args.v3.acConfig.ucTransmitterSel = 1;
949 				args.v3.acConfig.ucTransmitterSel = 2;
954 				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
957 					args.v3.acConfig.fCoherentMode = 1;
959 					args.v3.acConfig.fDualLinkConnector = 1;
1186 	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1251 			args.v3.sExtEncoder.ucAction = action;
1253 				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1255 				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
1256 			args.v3.sExtEncoder.ucEncoderMode =
1259 			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1261 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1263 					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1264 				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1266 				args.v3.sExtEncoder.ucLaneNum = 8;
1268 				args.v3.sExtEncoder.ucLaneNum = 4;
1271 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1274 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1277 				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1280 			args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
1429 	SELECT_CRTC_SOURCE_PARAMETERS_V3 v3;
1561 			args.v3.ucCRTC = amdgpu_crtc->crtc_id;
1576 			args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder);
1586 					args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1589 					args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1592 					args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1595 					args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1598 					args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1601 					args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1604 					args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1609 				args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1613 					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1615 					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1617 					args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1621 					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1623 					args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1625 					args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;