amd/amdgpu/atombios_crtc.c

39 				  struct drm_display_mode *mode,
55 		args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
56 		args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 		args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 		args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
61 		a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
62 		a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
65 			args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
66 			args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
68 			args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
69 			args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
190 				  struct drm_display_mode *mode)
200 	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
202 		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
203 	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
205 		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
207 		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
209 		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
211 		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
213 		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
217 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
219 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
221 	if (mode->flags & DRM_MODE_FLAG_CSYNC)
223 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
225 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 				    struct drm_display_mode *mode)
313 	u32 adjusted_clock = mode->clock;
315 	u32 dp_clock = mode->clock;
316 	u32 clock = mode->clock;
318 	bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
347 	/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
349 		adjusted_clock = mode->clock * 2;
747 			      struct drm_display_mode *mode)
770 		/* Assign mode clock for hdmi deep color max clock limit check */
771 		amdgpu_connector->pixelclock_for_modeset = mode->clock;
789 								 mode->clock / 10);
796 								 mode->clock / 10);
803 								 mode->clock / 10);
811 	amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
816 void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
823 	u32 pll_clock = mode->clock;
824 	u32 clock = mode->clock;