Lines Matching refs:ctx
63 struct atom_context *ctx;
74 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size);
75 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size);
110 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
121 temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
125 ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
165 ((ctx->
182 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
186 struct atom_context *gctx = ctx->ctx;
227 if (idx < ctx->ps_size)
228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
230 pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
268 if (idx < ctx->ws_size)
269 val = ctx->ws[idx];
271 pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
373 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
408 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
410 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
413 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
439 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
442 return atom_get_src_int(ctx,
448 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
450 atom_skip_src_int(ctx,
455 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
461 struct atom_context *gctx = ctx->ctx;
505 if (idx >= ctx->ps_size) {
506 pr_info("PS index out of range: %i > %i\n", idx, ctx->ps_size);
509 ctx->ps[idx] = cpu_to_le32(val);
541 if (idx >= ctx->ws_size) {
542 pr_info("WS index out of range: %i > %i\n", idx, ctx->ws_size);
545 ctx->ws[idx] = val;
599 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
605 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
607 src = atom_get_src(ctx, attr, ptr);
610 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
613 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
619 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
621 src = atom_get_src(ctx, attr, ptr);
624 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
627 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
632 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
641 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
642 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift, ctx->ps_size - ctx->ps_shift);
644 ctx->abort = true;
648 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
655 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
657 atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
660 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
665 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
667 src = atom_get_src(ctx, attr, ptr);
668 ctx->ctx->cs_equal = (dst == src);
669 ctx->ctx->cs_above = (dst > src);
670 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
671 ctx->ctx->cs_above ? "GT" : "LE");
674 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
686 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
691 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
693 src = atom_get_src(ctx, attr, ptr);
695 ctx->ctx->divmul[0] = dst / src;
696 ctx->ctx->divmul[1] = dst % src;
698 ctx->ctx->divmul[0] = 0;
699 ctx->ctx->divmul[1] = 0;
703 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
709 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
711 src = atom_get_src(ctx, attr, ptr);
714 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
716 ctx->ctx->divmul[0] = lower_32_bits(val64);
717 ctx->ctx->divmul[1] = upper_32_bits(val64);
719 ctx->ctx->divmul[0] = 0;
720 ctx->ctx->divmul[1] = 0;
724 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
729 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
737 execute = ctx->ctx->cs_above;
740 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
746 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
749 execute = !ctx->ctx->cs_above;
752 execute = ctx->ctx->cs_equal;
755 execute = !ctx->ctx->cs_equal;
762 if (ctx->last_jump == (ctx->start + target)) {
764 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
765 cjiffies -= ctx->last_jump_jiffies;
769 ctx->abort = true;
773 ctx->last_jump_jiffies = jiffies;
776 ctx->last_jump = ctx->start + target;
777 ctx->last_jump_jiffies = jiffies;
779 *ptr = ctx->start + target;
783 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
789 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
790 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
793 src = atom_get_src(ctx, attr, ptr);
797 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
800 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
806 atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
808 atom_skip_dst(ctx, arg, attr, ptr);
812 src = atom_get_src(ctx, attr, ptr);
814 atom_put_dst(ctx, arg, attr, &dptr, src, saved);
817 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
822 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
824 src = atom_get_src(ctx, attr, ptr);
825 ctx->ctx->divmul[0] = dst * src;
828 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
834 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
836 src = atom_get_src(ctx, attr, ptr);
838 ctx->ctx->divmul[0] = lower_32_bits(val64);
839 ctx->ctx->divmul[1] = upper_32_bits(val64);
842 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
847 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
853 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
855 src = atom_get_src(ctx, attr, ptr);
858 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
861 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
867 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
872 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
877 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
882 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
888 ctx->ctx->data_block = 0;
890 ctx->ctx->data_block = ctx->start;
892 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
893 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block);
896 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
900 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
903 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
914 ctx->ctx->io_mode = ATOM_IO_MM;
916 ctx->ctx->io_mode = ATOM_IO_IIO | port;
920 ctx->ctx->io_mode = ATOM_IO_PCI;
924 ctx->ctx->io_mode = ATOM_IO_SYSIO;
930 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
932 ctx->ctx->reg_block = U16(*ptr);
934 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
937 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
945 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
946 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
950 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
953 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
961 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
962 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
966 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
969 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
976 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
979 shift = atom_get_src(ctx, attr, ptr);
985 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
988 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
995 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
998 shift = atom_get_src(ctx, attr, ptr);
1004 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1007 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
1013 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1015 src = atom_get_src(ctx, attr, ptr);
1018 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1021 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
1026 src = atom_get_src(ctx, attr, ptr);
1032 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
1037 *ptr = ctx->start + target;
1048 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
1053 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1055 src = atom_get_src(ctx, attr, ptr);
1056 ctx->ctx->cs_equal = ((dst & src) == 0);
1057 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1060 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1066 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1068 src = atom_get_src(ctx, attr, ptr);
1071 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1074 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1080 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
1221 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size)
1223 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1239 ectx.ctx = ctx;
1286 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size)
1290 mutex_lock(&ctx->mutex);
1292 ctx->data_block = 0;
1294 ctx->reg_block = 0;
1296 ctx->fb_base = 0;
1298 ctx->io_mode = ATOM_IO_MM;
1300 ctx->divmul[0] = 0;
1301 ctx->divmul[1] = 0;
1302 r = amdgpu_atom_execute_table_locked(ctx, index, params, params_size);
1303 mutex_unlock(&ctx->mutex);
1309 static void atom_index_iio(struct atom_context *ctx, int base)
1311 ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1312 if (!ctx->iio)
1315 ctx->iio[CU8(base + 1)] = base + 2;
1323 static void atom_get_vbios_name(struct atom_context *ctx)
1335 p_rom = ctx->bios;
1345 memcpy(ctx->name, na, 7);
1346 ctx->name[7] = 0;
1364 memcpy(ctx->name, c_ptr, name_size);
1365 back = ctx->name + name_size;
1371 static void atom_get_vbios_date(struct atom_context *ctx)
1376 p_rom = ctx->bios;
1380 ctx->date[0] = '2';
1381 ctx->date[1] = '0';
1382 ctx->date[2] = date_in_rom[6];
1383 ctx->date[3] = date_in_rom[7];
1384 ctx->date[4] = '/';
1385 ctx->date[5] = date_in_rom[0];
1386 ctx->date[6] = date_in_rom[1];
1387 ctx->date[7] = '/';
1388 ctx->date[8] = date_in_rom[3];
1389 ctx->date[9] = date_in_rom[4];
1390 ctx->date[10] = ' ';
1391 ctx->date[11] = date_in_rom[9];
1392 ctx->date[12] = date_in_rom[10];
1393 ctx->date[13] = date_in_rom[11];
1394 ctx->date[14] = date_in_rom[12];
1395 ctx->date[15] = date_in_rom[13];
1396 ctx->date[16] = '\0';
1399 static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start,
1408 p_rom = ctx->bios;
1422 static void atom_get_vbios_pn(struct atom_context *ctx)
1430 p_rom = ctx->bios;
1442 vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64);
1453 ctx->vbios_pn[count] = vbios_str[count];
1457 ctx->vbios_pn[count] = 0;
1460 pr_info("ATOM BIOS: %s\n", ctx->vbios_pn);
1463 static void atom_get_vbios_version(struct atom_context *ctx)
1469 p_rom = ctx->bios;
1485 atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, start, end, 64);
1489 memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
1491 ctx->vbios_ver_str[0] = '\0';
1498 struct atom_context *ctx =
1504 if (!ctx)
1507 ctx->card = card;
1508 ctx->bios = bios;
1512 kfree(ctx);
1519 kfree(ctx);
1528 kfree(ctx);
1532 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1533 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1534 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1535 if (!ctx->iio) {
1536 amdgpu_atom_destroy(ctx);
1547 ctx->version = atom_fw_info->ulFirmwareRevision;
1551 atom_get_vbios_name(ctx);
1552 atom_get_vbios_pn(ctx);
1553 atom_get_vbios_date(ctx);
1554 atom_get_vbios_version(ctx);
1556 return ctx;
1559 int amdgpu_atom_asic_init(struct atom_context *ctx)
1561 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1572 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1574 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps, 16);
1583 void amdgpu_atom_destroy(struct atom_context *ctx)
1585 kfree(ctx->iio);
1586 kfree(ctx);
1589 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1594 int idx = CU16(ctx->data_table + offset);
1595 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1610 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
1614 int idx = CU16(ctx->cmd_table + offset);
1615 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);