Lines Matching refs:ring
71 uint32_t inst_idx, struct amdgpu_ring *ring)
77 ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
83 switch (ring->funcs->type) {
99 DRM_ERROR("Not support ring type %d!", ring->funcs->type);
105 ring->xcp_id = xcp_id;
113 struct amdgpu_ring *ring,
119 .gpu_sched[ring->funcs->type][ring->hw_prio].num_scheds;
120 adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[ring->funcs->type][ring->hw_prio]
121 .sched[(*num_gpu_sched)++] = &ring->sched;
122 DRM_DEBUG("%s :[%d] gpu_sched[%d][%d] = %d", ring->name,
123 sel_xcp_id, ring->funcs->type,
124 ring->hw_prio, *num_gpu_sched);
130 struct amdgpu_ring *ring;
142 ring = adev->rings[i];
143 if (!ring || !ring->sched.ready || ring->no_scheduler)
146 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
151 if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
152 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
154 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);
165 struct amdgpu_ring *ring = adev->rings[i];
167 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ||
168 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
169 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring);
171 aqua_vanjaram_set_xcp_id(adev, ring->me, ring);