amd/amdgpu/amdgpu_virt.c

83 	struct amdgpu_virt *virt = &adev->virt;
86 	if (virt->ops && virt->ops->req_full_gpu) {
87 		r = virt->ops->req_full_gpu(adev, init);
91 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
106 	struct amdgpu_virt *virt = &adev->virt;
109 	if (virt->ops && virt->ops->rel_full_gpu) {
110 		r = virt->ops->rel_full_gpu(adev, init);
114 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
127 	struct amdgpu_virt *virt = &adev->virt;
130 	if (virt->ops && virt->ops->reset_gpu) {
131 		r = virt->ops->reset_gpu(adev);
135 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
143 	struct amdgpu_virt *virt = &adev->virt;
145 	if (virt->ops && virt->ops->req_init_data)
146 		virt->ops->req_init_data(adev);
148 	if (adev->virt.req_init_data_ver > 0)
162 	struct amdgpu_virt *virt = &adev->virt;
164 	if (!virt->ops || !virt->ops->wait_reset)
167 	return virt->ops->wait_reset(adev);
180 	if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
186 				    &adev->virt.mm_table.bo,
187 				    &adev->virt.mm_table.gpu_addr,
188 				    (void *)&adev->virt.mm_table.cpu_addr);
194 	memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
196 		 adev->virt.mm_table.gpu_addr,
197 		 adev->virt.mm_table.cpu_addr);
208 	if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
211 	amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
212 			      &adev->virt.mm_table.gpu_addr,
213 			      (void *)&adev->virt.mm_table.cpu_addr);
214 	adev->virt.mm_table.gpu_addr = 0;
240 	struct amdgpu_virt *virt = &adev->virt;
241 	struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
266 	virt->ras_init_done = true;
280 	struct amdgpu_virt *virt = &adev->virt;
281 	struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
300 	struct amdgpu_virt *virt = &adev->virt;
301 	struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
303 	virt->ras_init_done = false;
313 	virt->virt_eh_data = NULL;
319 	struct amdgpu_virt *virt = &adev->virt;
320 	struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
331 	struct amdgpu_virt *virt = &adev->virt;
332 	struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
370 	struct amdgpu_virt *virt = &adev->virt;
371 	struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
416 	struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
423 	if (adev->virt.fw_reserve.p_pf2vf == NULL)
435 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
436 			adev->virt.fw_reserve.checksum_key, checksum);
442 		adev->virt.gim_feature =
449 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
456 		adev->virt.vf2pf_update_interval_ms =
458 		adev->virt.gim_feature =
460 		adev->virt.reg_access =
463 		adev->virt.decode_max_dimension_pixels = 0;
464 		adev->virt.decode_max_frame_pixels = 0;
465 		adev->virt.encode_max_dimension_pixels = 0;
466 		adev->virt.encode_max_frame_pixels = 0;
467 		adev->virt.is_mm_bw_enabled = false;
470 			adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
473 			adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
476 			adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
479 			adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
481 		if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
482 			adev->virt.is_mm_bw_enabled = true;
493 	if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
494 		adev->virt.vf2pf_update_interval_ms = 2000;
502 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
504 	if (adev->virt.fw_reserve.p_vf2pf == NULL)
537 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
539 	if (adev->virt.fw_reserve.p_vf2pf == NULL)
583 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
592 	schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
597 	if (adev->virt.vf2pf_update_interval_ms != 0) {
599 		cancel_delayed_work_sync(&adev->virt.vf2pf_work);
600 		adev->virt.vf2pf_update_interval_ms = 0;
606 	adev->virt.fw_reserve.p_pf2vf = NULL;
607 	adev->virt.fw_reserve.p_vf2pf = NULL;
608 	adev->virt.vf2pf_update_interval_ms = 0;
616 		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
617 		schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
620 		adev->virt.fw_reserve.p_pf2vf =
637 			adev->virt.fw_reserve.p_pf2vf =
640 			adev->virt.fw_reserve.p_vf2pf =
644 			adev->virt.fw_reserve.p_pf2vf =
647 			adev->virt.fw_reserve.p_vf2pf =
656 		if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
657 			pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
663 			if (bp_block_size && !adev->virt.ras_init_done)
666 			if (adev->virt.ras_init_done)
697 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
700 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
705 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
712 		adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
767 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
777 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
877 	if (!adev->virt.is_mm_bw_enabled)
882 			encode[i].max_width = adev->virt.encode_max_dimension_pixels;
883 			encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
893 			decode[i].max_width = adev->virt.decode_max_dimension_pixels;
894 			decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;