amd/amdgpu/amdgpu_ras.c

209 	struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
211 		.head = obj->head,
216 	if (amdgpu_ras_query_error_status(obj->adev, &info))
220 	if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
221 	    amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
222 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
223 			dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
622 	struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
624 		.head = obj->head,
627 	if (!amdgpu_ras_get_error_query_ready(obj->adev))
630 	if (amdgpu_ras_query_error_status(obj->adev, &info))
633 	if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
634 	    amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
635 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
636 			dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
647 /* obj begin */
649 #define get_obj(obj) do { (obj)->use++; } while (0)
650 #define alive_obj(obj) ((obj)->use)
652 static inline void put_obj(struct ras_manager *obj)
654 	if (obj && (--obj->use == 0)) {
655 		list_del(&obj->node);
656 		amdgpu_ras_error_data_fini(&obj->err_data);
659 	if (obj && (obj->use < 0))
660 		DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
663 /* make one obj and return it. */
668 	struct ras_manager *obj;
680 		obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
682 		obj = &con->objs[head->block];
684 	/* already exist. return obj? */
685 	if (alive_obj(obj))
688 	if (amdgpu_ras_error_data_init(&obj->err_data))
691 	obj->head = *head;
692 	obj->adev = adev;
693 	list_add(&obj->node, &con->head);
694 	get_obj(obj);
696 	return obj;
699 /* return an obj equal to head, or the first when head is NULL */
704 	struct ras_manager *obj;
718 			obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
720 			obj = &con->objs[head->block];
722 		if (alive_obj(obj))
723 			return obj;
726 			obj = &con->objs[i];
727 			if (alive_obj(obj))
728 				return obj;
734 /* obj end */
752  * if obj is not created, then create one.
759 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
761 	/* If hardware does not support ras, then do not create obj.
762 	 * But if hardware support ras, we can create the obj.
771 		if (!obj) {
772 			obj = amdgpu_ras_create_obj(adev, head);
773 			if (!obj)
776 			/* In case we create obj somewhere else */
777 			get_obj(obj);
781 		if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
783 			put_obj(obj);
841 	/* setup the obj */
903 	struct ras_manager *obj, *tmp;
905 	list_for_each_entry_safe(obj, tmp, &con->head, node) {
907 		 * aka just release the obj and corresponding flags
910 			if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
913 			if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
941 			 * so just create the obj
961 			 * so just create the obj
991 	struct amdgpu_ras_block_object *obj;
1002 		obj = node->ras_obj;
1003 		if (obj->ras_block_match) {
1004 			if (obj->ras_block_match(obj, block, sub_block_index) == 0)
1005 				return obj;
1007 			if (amdgpu_ras_block_match_default(obj, block) == 0)
1008 				return obj;
1215 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1223 			amdgpu_ras_error_statistic_de_count(&obj->err_data,
1225 			amdgpu_ras_error_statistic_ce_count(&obj->err_data,
1227 			amdgpu_ras_error_statistic_ue_count(&obj->err_data,
1232 		obj->err_data.ue_count += err_data->ue_count;
1233 		obj->err_data.ce_count += err_data->ce_count;
1234 		obj->err_data.de_count += err_data->de_count;
1251 	struct ras_manager *obj;
1257 	obj = get_ras_manager(adev, blk);
1258 	if (!obj)
1261 	return amdgpu_aca_add_handle(adev, &obj->aca_handle, ras_block_str(blk), aca_info, data);
1266 	struct ras_manager *obj;
1268 	obj = get_ras_manager(adev, blk);
1269 	if (!obj)
1272 	amdgpu_aca_remove_handle(&obj->aca_handle);
1281 	struct ras_manager *obj;
1283 	obj = get_ras_manager(adev, blk);
1284 	if (!obj)
1287 	return amdgpu_aca_get_error_data(adev, &obj->aca_handle, type, err_data, qctx);
1293 	struct ras_manager *obj = container_of(handle, struct ras_manager, aca_handle);
1295 		.head = obj->head,
1298 	if (amdgpu_ras_query_error_status(obj->adev, &info))
1368 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1374 	if (!obj)
1394 	amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1396 	info->ue_count = obj->err_data.ue_count;
1397 	info->ce_count = obj->err_data.ce_count;
1398 	info->de_count = obj->err_data.de_count;
1468 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1485 	if (!obj)
1580 	struct ras_manager *obj;
1596 		list_for_each_entry(obj, &con->head, node) {
1598 				.head = obj->head,
1760 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1762 	if (!obj || obj->attr_inuse)
1765 	get_obj(obj);
1767 	snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1770 	obj->sysfs_attr = (struct device_attribute){
1772 			.name = obj->fs_data.sysfs_name,
1777 	sysfs_attr_init(&obj->sysfs_attr.attr);
1780 				&obj->sysfs_attr.attr,
1782 		put_obj(obj);
1786 	obj->attr_inuse = 1;
1794 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1796 	if (!obj || !obj->attr_inuse)
1801 				&obj->sysfs_attr.attr,
1803 	obj->attr_inuse = 0;
1804 	put_obj(obj);
1812 	struct ras_manager *obj, *tmp;
1814 	list_for_each_entry_safe(obj, tmp, &con->head, node) {
1815 		amdgpu_ras_sysfs_remove(adev, &obj->head);
1893 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1895 	if (!obj || !dir)
1898 	get_obj(obj);
1900 	memcpy(obj->fs_data.debugfs_name,
1902 			sizeof(obj->fs_data.debugfs_name));
1904 	debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1905 			    obj, &amdgpu_ras_debugfs_ops);
1912 	struct ras_manager *obj;
1924 	list_for_each_entry(obj, &con->head, node) {
1925 		if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1926 			(obj->attr_inuse == 1)) {
1928 					get_ras_block_str(&obj->head));
1929 			fs_info.head = obj->head;
2039 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
2043 	struct amdgpu_device *adev = obj->adev;
2045 		amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
2065 	amdgpu_umc_poison_handler(adev, obj->head.block, 0);
2080 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
2083 	dev_info(obj->adev->dev,
2086 	if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
2087 		struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev);
2089 		amdgpu_ras_put_poison_req(obj->adev,
2098 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
2101 	struct ras_ih_data *data = &obj->ih_data;
2115 	ret = data->cb(obj->adev, &err_data, entry);
2125 		obj->err_data.ue_count += err_data.ue_count;
2126 		obj->err_data.ce_count += err_data.ce_count;
2127 		obj->err_data.de_count += err_data.de_count;
2133 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
2135 	struct ras_ih_data *data = &obj->ih_data;
2147 		if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
2148 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2149 				amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
2151 				amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
2153 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2154 				amdgpu_ras_interrupt_umc_handler(obj, &entry);
2156 				dev_warn(obj->adev->dev,
2166 	struct ras_manager *obj =
2169 	amdgpu_ras_interrupt_handler(obj);
2175 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
2176 	struct ras_ih_data *data = &obj->ih_data;
2178 	if (!obj)
2200 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2203 	if (!obj)
2206 	data = &obj->ih_data;
2214 	put_obj(obj);
2222 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2226 	if (!obj) {
2228 		obj = amdgpu_ras_create_obj(adev, head);
2229 		if (!obj)
2232 		get_obj(obj);
2236 	data = &obj->ih_data;
2253 		put_obj(obj);
2266 	struct ras_manager *obj, *tmp;
2268 	list_for_each_entry_safe(obj, tmp, &con->head, node) {
2269 		amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2280 	struct ras_manager *obj;
2285 	list_for_each_entry(obj, &con->head, node) {
2287 			.head = obj->head,
2355 	struct ras_manager *obj;
2360 	list_for_each_entry(obj, &con->head, node) {
2362 			.head = obj->head,
3566 	struct ras_manager *obj, *tmp;
3587 		list_for_each_entry_safe(obj, tmp, &con->head, node) {
3588 			if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3589 				amdgpu_ras_feature_enable(adev, &obj->head, 0);
3591 				WARN_ON(alive_obj(obj));
3613 	struct amdgpu_ras_block_object *obj;
3636 		obj = node->ras_obj;
3637 		if (!obj) {
3642 		if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block))
3645 		if (obj->ras_late_init) {
3646 			r = obj->ras_late_init(adev, &obj->ras_comm);
3649 					obj->ras_comm.name, r);
3653 			amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3678 	struct amdgpu_ras_block_object *obj = NULL;
3686 			obj = ras_node->ras_obj;
3687 			if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3688 			    obj->ras_fini)
3689 				obj->ras_fini(adev, &obj->ras_comm);
3691 				amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);