amd/amdgpu/amdgpu_jpeg.c

37 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
41 	INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
42 	mutex_init(&adev->jpeg.jpeg_pg_lock);
43 	atomic_set(&adev->jpeg.total_submission_cnt, 0);
45 	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
46 	    (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
47 		adev->jpeg.indirect_sram = true;
49 	for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
50 		if (adev->jpeg.harvest_config & (1 << i))
53 		if (adev->jpeg.indirect_sram) {
54 			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
57 					&adev->jpeg.inst[i].dpg_sram_bo,
58 					&adev->jpeg.inst[i].dpg_sram_gpu_addr,
59 					&adev->jpeg.inst[i].dpg_sram_cpu_addr);
61 				dev_err(adev->dev,
71 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
75 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
76 		if (adev->jpeg.harvest_config & (1 << i))
80 			&adev->jpeg.inst[i].dpg_sram_bo,
81 			&adev->jpeg.inst[i].dpg_sram_gpu_addr,
82 			(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
84 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
85 			amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
88 	mutex_destroy(&adev->jpeg.jpeg_pg_lock);
93 int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
95 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
100 int amdgpu_jpeg_resume(struct amdgpu_device *adev)
107 	struct amdgpu_device *adev =
112 	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
113 		if (adev->jpeg.harvest_config & (1 << i))
116 		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
117 			fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
120 	if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
121 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
124 		schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
129 	struct amdgpu_device *adev = ring->adev;
131 	atomic_inc(&adev->jpeg.total_submission_cnt);
132 	cancel_delayed_work_sync(&adev->jpeg.idle_work);
134 	mutex_lock(&adev->jpeg.jpeg_pg_lock);
135 	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
137 	mutex_unlock(&adev->jpeg.jpeg_pg_lock);
142 	atomic_dec(&ring->adev->jpeg.total_submission_cnt);
143 	schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
148 	struct amdgpu_device *adev = ring->adev;
154 	if (amdgpu_sriov_vf(adev))
161 	WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
163 	RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
165 	amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
169 	for (i = 0; i < adev->usec_timeout; i++) {
170 		tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
176 	if (i >= adev->usec_timeout)
185 	struct amdgpu_device *adev = ring->adev;
192 	r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
199 	ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
224 	struct amdgpu_device *adev = ring->adev;
244 	if (!amdgpu_sriov_vf(adev)) {
245 		for (i = 0; i < adev->usec_timeout; i++) {
246 			tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
254 		if (i >= adev->usec_timeout)
263 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
267 	struct ras_common_if *ras_if = adev->jpeg.ras_if;
276 	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
281 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
285 	r = amdgpu_ras_block_late_init(adev, ras_block);
289 	if (amdgpu_ras_is_supported(adev, ras_block->block)) {
290 		for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
291 			if (adev->jpeg.harvest_config & (1 << i) ||
292 			    !adev->jpeg.inst[i].ras_poison_irq.funcs)
295 			r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
303 	amdgpu_ras_block_late_fini(adev, ras_block);
307 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
312 	if (!adev->jpeg.ras)
315 	ras = adev->jpeg.ras;
316 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
318 		dev_err(adev->dev, "Failed to register jpeg ras block!\n");
325 	adev->jpeg.ras_if = &ras->ras_block.ras_comm;
333 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
338 		.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
339 		.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
340 			      (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
343 	return psp_execute_ip_fw_load(&adev->psp, &ucode);