amd/amdgpu/amdgpu_ih.c

33  * @ih: ih ring to initialize
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
50 	ih->ring_size = ring_size;
51 	ih->ptr_mask = ih->ring_size - 1;
52 	ih->rptr = 0;
53 	ih->use_bus_addr = use_bus_addr;
58 		if (ih->ring)
64 		ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
66 		if (ih->ring == NULL)
69 		ih->gpu_addr = dma_addr;
70 		ih->wptr_addr = dma_addr + ih->ring_size;
71 		ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
72 		ih->rptr_addr = dma_addr + ih->ring_size + 4;
73 		ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
87 		r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
89 					    &ih->ring_obj, &ih->gpu_addr,
90 					    (void **)&ih->ring);
97 		ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
98 		ih->wptr_cpu = &adev->wb.wb[wptr_offs];
99 		ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
100 		ih->rptr_cpu = &adev->wb.wb[rptr_offs];
103 	init_waitqueue_head(&ih->wait_process);
111  * @ih: ih ring to tear down
116 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
119 	if (!ih->ring)
122 	if (ih->use_bus_addr) {
127 		dma_free_coherent(adev->dev, ih->ring_size + 8,
128 				  (void *)ih->ring, ih->gpu_addr);
129 		ih->ring = NULL;
131 		amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
132 				      (void **)&ih->ring);
133 		amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
134 		amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
142  * @ih: ih ring to write to
149 void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
152 	uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
156 	        ih->ring[wptr++] = cpu_to_le32(iv[i]);
159 	wptr &= ih->ptr_mask;
162 	if (wptr != READ_ONCE(ih->rptr)) {
164 		WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
167 			      wptr, ih->rptr);
175  * @ih: ih ring to process
180 					struct amdgpu_ih_ring *ih)
186 	if (!ih->enabled || adev->shutdown)
189 	checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
192 	checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
194 	return wait_event_interruptible_timeout(ih->wait_process,
195 		    amdgpu_ih_ts_after(checkpoint_ts, ih->processed_timestamp) ||
196 		    ih->rptr == amdgpu_ih_get_wptr(adev, ih), timeout);
203  * @ih: ih ring to process
208 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
213 	if (!ih->enabled || adev->shutdown)
216 	wptr = amdgpu_ih_get_wptr(adev, ih);
220 	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
225 	while (ih->rptr != wptr && --count) {
226 		amdgpu_irq_dispatch(adev, ih);
227 		ih->rptr &= ih->ptr_mask;
230 	amdgpu_ih_set_rptr(adev, ih);
231 	wake_up_all(&ih->wait_process);
234 	wptr = amdgpu_ih_get_wptr(adev, ih);
235 	if (wptr != ih->rptr)
245  * @ih: ih ring to process
253 				struct amdgpu_ih_ring *ih,
257 	u32 ring_index = ih->rptr >> 2;
260 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
261 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
262 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
263 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
264 	dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
265 	dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
266 	dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
267 	dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
284 	ih->rptr += 32;
287 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
295 	ring_index = (rptr & ih->ptr_mask) >> 2;
297 	dw1 = le32_to_cpu(ih->ring[ring_index + 1]);
298 	dw2 = le32_to_cpu(ih->ring[ring_index + 2]);