amd/amdgpu/amdgpu_ib.c

45  * command ring and the hw will fetch the commands from the IB
48  * put in IBs for execution by the requested ring.
105  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
107  * @ring: ring index the IB is associated with
113  * Schedule an IB on the associated ring (all asics).
116  * On SI, there are two parallel engines fed from the primary ring,
123  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
126 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
130 	struct amdgpu_device *adev = ring->adev;
150 	/* ring tests don't use a job */
168 	if (!ring->sched.ready && !ring->is_mes_queue) {
169 		dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
173 	if (vm && !job->vmid && !ring->is_mes_queue) {
179 	    (!ring->funcs->secure_submission_supported)) {
180 		dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
184 	alloc_size = ring->funcs->emit_frame_size + num_ibs *
185 		ring->funcs->emit_ib_size;
187 	r = amdgpu_ring_alloc(ring, alloc_size);
193 	need_ctx_switch = ring->current_ctx != fence_ctx;
194 	if (ring->funcs->emit_pipeline_sync && job &&
197 	     amdgpu_vm_need_pipeline_sync(ring, job))) {
206 	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
207 		ring->funcs->emit_mem_sync(ring);
209 	if (ring->funcs->emit_wave_limit &&
210 	    ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
211 		ring->funcs->emit_wave_limit(ring, true);
213 	if (ring->funcs->insert_start)
214 		ring->funcs->insert_start(ring);
217 		r = amdgpu_vm_flush(ring, job, need_pipe_sync);
219 			amdgpu_ring_undo(ring);
224 	amdgpu_ring_ib_begin(ring);
226 	if (ring->funcs->emit_gfx_shadow)
227 		amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
230 	if (ring->funcs->init_cond_exec)
231 		cond_exec = amdgpu_ring_init_cond_exec(ring,
232 						       ring->cond_exe_gpu_addr);
234 	amdgpu_device_flush_hdp(adev, ring);
239 	if (job && ring->funcs->emit_cntxcntl) {
242 		amdgpu_ring_emit_cntxcntl(ring, status);
248 	if (job && ring->funcs->emit_frame_cntl) {
250 		amdgpu_ring_emit_frame_cntl(ring, true, secure);
256 		if (job && ring->funcs->emit_frame_cntl) {
258 				amdgpu_ring_emit_frame_cntl(ring, false, secure);
260 				amdgpu_ring_emit_frame_cntl(ring, true, secure);
264 		amdgpu_ring_emit_ib(ring, job, ib, status);
268 	if (job && ring->funcs->emit_frame_cntl)
269 		amdgpu_ring_emit_frame_cntl(ring, false, secure);
271 	amdgpu_device_invalidate_hdp(adev, ring);
278 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
282 	if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {
283 		amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
284 		amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);
287 	r = amdgpu_fence_emit(ring, f, job, fence_flags);
291 			amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid);
292 		amdgpu_ring_undo(ring);
296 	if (ring->funcs->insert_end)
297 		ring->funcs->insert_end(ring);
299 	amdgpu_ring_patch_cond_exec(ring, cond_exec);
301 	ring->current_ctx = fence_ctx;
302 	if (vm && ring->funcs->emit_switch_buffer)
303 		amdgpu_ring_emit_switch_buffer(ring);
305 	if (ring->funcs->emit_wave_limit &&
306 	    ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
307 		ring->funcs->emit_wave_limit(ring, false);
309 	amdgpu_ring_ib_end(ring);
310 	amdgpu_ring_commit(ring);
372  * Test an IB (Indirect Buffer) on each ring.
373  * If the test fails, disable the ring.
374  * Returns 0 on success, error if the primary GFX ring
405 		struct amdgpu_ring *ring = adev->rings[i];
411 		if (!ring->sched.ready || !ring->funcs->test_ib)
415 		    ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
419 		if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
420 			ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
421 			ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
422 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
423 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
424 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
429 		r = amdgpu_ring_test_ib(ring, tmo);
432 				      ring->name);
436 		ring->sched.ready = false;
438 			  ring->name, r);
440 		if (ring == &adev->gfx.gfx_ring[0]) {