Lines Matching refs:queue

44 				int pipe, int queue)
51 bit += queue;
57 int *mec, int *pipe, int *queue)
59 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
68 int xcc_id, int mec, int pipe, int queue)
70 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
75 int me, int pipe, int queue)
82 bit += queue;
88 int *me, int *pipe, int *queue)
90 *queue = bit % adev->gfx.me.num_queue_per_pipe;
98 int me, int pipe, int queue)
100 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
176 int queue = ring->queue;
179 /* Policy: use pipe1 queue0 as high priority graphics queue if we
183 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
187 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
198 /* Policy: use 1st queue as high priority compute queue if we
199 * have more than one compute queue.
210 int i, j, queue, pipe;
223 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
226 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
239 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
246 int i, queue, pipe;
252 /* policy: amdgpu owns the first queue per pipe at this stage
256 queue = (i / adev->gfx.me.num_pipe_per_me) %
259 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
276 int mec, pipe, queue;
286 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
290 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
291 * only can be issued on queue 0.
293 if ((mec == 1 && pipe > 1) || queue != 0)
298 ring->queue = queue;
303 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
333 xcc_id, ring->me, ring->pipe, ring->queue);
380 /* create MQD for each compute/gfx queue */
591 int mec, pipe, queue;
594 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
596 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
627 kiq_ring->queue);
1075 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");