Lines Matching defs:sdma_rlc_reg_offset
268 uint32_t sdma_rlc_reg_offset;
272 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
273 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
278 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
295 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
297 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
300 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
302 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
303 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
305 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
307 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
312 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
377 uint32_t sdma_rlc_reg_offset;
381 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
383 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
499 uint32_t sdma_rlc_reg_offset;
504 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
506 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
508 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
511 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
521 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
522 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
523 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
526 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);