amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

88 	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
89 	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
120 	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
202 		value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
205 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
210 	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
213 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
214 		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
220 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
249 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
251 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
253 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
255 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
259 		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
264 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
269 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
338 		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\
347 	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
348 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
468 	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
473 		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
474 		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
513 		WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
530 	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
534 		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
597 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
598 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
607 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
641 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
643 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
650 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
652 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),