Lines Matching defs:sdma_rlc_reg_offset
63 uint32_t sdma_rlc_reg_offset;
70 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
73 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
78 data = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
88 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL_OFFSET,
93 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, data);
94 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR,
96 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI,
99 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 1);
101 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
103 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
106 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR,
108 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR_HI,
111 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 0);
113 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
114 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE_HI,
116 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_LO,
118 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_ADDR_HI,
123 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, data);
132 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
149 DUMP_REG(sdma_rlc_reg_offset + reg);
151 DUMP_REG(sdma_rlc_reg_offset + reg);
154 DUMP_REG(sdma_rlc_reg_offset + reg);
157 DUMP_REG(sdma_rlc_reg_offset + reg);
168 uint32_t sdma_rlc_reg_offset;
172 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
175 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
187 uint32_t sdma_rlc_reg_offset;
192 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
195 temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);
197 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, temp);
200 temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);
210 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, 0);
211 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL,
212 RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL) |
216 RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR);
218 RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI);