Lines Matching defs:sdma_rlc_reg_offset
73 uint32_t sdma_rlc_reg_offset;
115 sdma_rlc_reg_offset = sdma_engine_reg_base
119 queue_id, sdma_rlc_reg_offset);
121 return sdma_rlc_reg_offset;
128 uint32_t sdma_rlc_reg_offset;
135 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
138 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
143 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
153 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
158 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
159 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
161 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
164 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
166 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
168 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
171 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
173 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
176 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
178 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
179 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
181 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
183 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
188 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
197 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
208 DUMP_REG(sdma_rlc_reg_offset + reg);
210 DUMP_REG(sdma_rlc_reg_offset + reg);
213 DUMP_REG(sdma_rlc_reg_offset + reg);
216 DUMP_REG(sdma_rlc_reg_offset + reg);
228 uint32_t sdma_rlc_reg_offset;
232 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
235 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
247 uint32_t sdma_rlc_reg_offset;
252 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
255 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
257 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
260 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
270 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
271 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
272 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
275 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
277 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);