Lines Matching refs:gpio
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
117 * struct zynq_gpio - gpio device private data structure
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
159 * @gpio: Pointer to driver data struct
163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
170 * @gpio: Pointer to driver data struct
174 static int gpio_data_ro_bug(struct zynq_gpio *gpio)
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
186 * for the given gpio pin
187 * @gpio: gpio device data structure
194 struct zynq_gpio *gpio)
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
199 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
200 (pin_num <= gpio->p_data->bank_max[bank])) {
203 gpio->p_data->bank_min[bank];
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
219 * @pin: gpio pin number within the device
229 struct zynq_gpio *gpio = gpiochip_get_data(chip);
231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
233 if (gpio_data_ro_bug(gpio)) {
234 if (zynq_gpio_is_zynq(gpio)) {
236 data = readl_relaxed(gpio->base_addr +
239 data = readl_relaxed(gpio->base_addr +
244 data = readl_relaxed(gpio->base_addr +
247 data = readl_relaxed(gpio->base_addr +
252 data = readl_relaxed(gpio->base_addr +
261 * @pin: gpio pin number within the device
266 * gpio pin to the specified value. The state is either 0 or non-zero.
272 struct zynq_gpio *gpio = gpiochip_get_data(chip);
274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
292 writel_relaxed(state, gpio->base_addr + reg_offset);
298 * @pin: gpio pin number within the device
301 * the gpio pin as input.
310 struct zynq_gpio *gpio = gpiochip_get_data(chip);
312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
323 spin_lock_irqsave(&gpio->dirlock, flags);
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
327 spin_unlock_irqrestore(&gpio->dirlock, flags);
335 * @pin: gpio pin number within the device
350 struct zynq_gpio *gpio = gpiochip_get_data(chip);
352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
355 spin_lock_irqsave(&gpio->dirlock, flags);
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
364 spin_unlock_irqrestore(&gpio->dirlock, flags);
374 * @pin: gpio pin number within the device
384 struct zynq_gpio *gpio = gpiochip_get_data(chip);
386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
400 * This function calculates gpio pin number from irq number and sets the
409 struct zynq_gpio *gpio =
414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
416 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
420 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
421 * @irq_data: irq data containing irq number of gpio pin for the interrupt
424 * This function calculates the gpio pin number from irq number and sets the
433 struct zynq_gpio *gpio =
438 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
440 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
444 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
445 * @irq_data: irq data containing irq number of gpio pin for the interrupt
448 * This function calculates gpio pin number from irq number and sets the bit
454 struct zynq_gpio *gpio =
458 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
460 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
464 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
465 * @irq_data: irq data containing irq number of gpio pin for the interrupt
487 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
488 * @irq_data: irq data containing irq number of gpio pin
489 * @type: interrupt type that is to be set for the gpio pin
491 * This function gets the gpio pin number and its bank from the gpio pin number
505 struct zynq_gpio *gpio =
509 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
511 int_type = readl_relaxed(gpio->base_addr +
513 int_pol = readl_relaxed(gpio->base_addr +
515 int_any = readl_relaxed(gpio->base_addr +
550 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
552 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
554 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
570 struct zynq_gpio *gpio =
573 irq_set_irq_wake(gpio->irq, on);
626 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
630 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
631 struct irq_domain *irqdomain = gpio->chip.irq.domain;
642 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
646 * gpio pin number which has triggered an interrupt. It then acks the triggered
649 * Note: A bug is reported if no handler is set for the gpio pin.
655 struct zynq_gpio *gpio =
661 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
662 int_sts = readl_relaxed(gpio->base_addr +
664 int_enb = readl_relaxed(gpio->base_addr +
666 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
667 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
674 static void zynq_gpio_save_context(struct zynq_gpio *gpio)
678 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
679 gpio->context.datalsw[bank_num] =
680 readl_relaxed(gpio->base_addr +
682 gpio->context.datamsw[bank_num] =
683 readl_relaxed(gpio->base_addr +
685 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
687 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
689 gpio->context.int_type[bank_num] =
690 readl_relaxed(gpio->base_addr +
692 gpio->context.int_polarity[bank_num] =
693 readl_relaxed(gpio->base_addr +
695 gpio->context.int_any[bank_num] =
696 readl_relaxed(gpio->base_addr +
698 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
703 static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
707 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
708 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
710 writel_relaxed(gpio->context.datalsw[bank_num],
711 gpio->base_addr +
713 writel_relaxed(gpio->context.datamsw[bank_num],
714 gpio->base_addr +
716 writel_relaxed(gpio->context.dirm[bank_num],
717 gpio->base_addr +
719 writel_relaxed(gpio->context.int_type[bank_num],
720 gpio->base_addr +
722 writel_relaxed(gpio->context.int_polarity[bank_num],
723 gpio->base_addr +
725 writel_relaxed(gpio->context.int_any[bank_num],
726 gpio->base_addr +
728 writel_relaxed(~(gpio->context.int_en[bank_num]),
729 gpio->base_addr +
731 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
738 struct zynq_gpio *gpio = dev_get_drvdata(dev);
739 struct irq_data *data = irq_get_irq_data(gpio->irq);
747 disable_irq(gpio->irq);
750 zynq_gpio_save_context(gpio);
759 struct zynq_gpio *gpio = dev_get_drvdata(dev);
760 struct irq_data *data = irq_get_irq_data(gpio->irq);
769 enable_irq(gpio->irq);
773 zynq_gpio_restore_context(gpio);
782 struct zynq_gpio *gpio = dev_get_drvdata(dev);
784 clk_disable_unprepare(gpio->clk);
791 struct zynq_gpio *gpio = dev_get_drvdata(dev);
793 return clk_prepare_enable(gpio->clk);
880 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
881 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
882 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
883 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
892 * This function allocates memory resources for the gpio device and registers
893 * all the banks of the device. It will also set up interrupts for the gpio
902 struct zynq_gpio *gpio;
907 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
908 if (!gpio)
916 gpio->p_data = match->data;
917 platform_set_drvdata(pdev, gpio);
919 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
920 if (IS_ERR(gpio->base_addr))
921 return PTR_ERR(gpio->base_addr);
923 gpio->irq = platform_get_irq(pdev, 0);
924 if (gpio->irq < 0)
925 return gpio->irq;
927 /* configure the gpio chip */
928 chip = &gpio->chip;
929 chip->label = gpio->p_data->label;
939 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
940 chip->ngpio = gpio->p_data->ngpio;
943 gpio->clk = devm_clk_get(&pdev->dev, NULL);
944 if (IS_ERR(gpio->clk))
945 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
947 ret = clk_prepare_enable(gpio->clk);
953 spin_lock_init(&gpio->dirlock);
962 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
963 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
965 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
981 girq->parents[0] = gpio->irq;
985 /* report a bug if gpio chip registration fails */
986 ret = gpiochip_add_data(chip, gpio);
988 dev_err(&pdev->dev, "Failed to add gpio chip\n");
992 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
1002 clk_disable_unprepare(gpio->clk);
1015 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1021 gpiochip_remove(&gpio->chip);
1022 clk_disable_unprepare(gpio->clk);