Lines Matching refs:gc
39 * @gc: gpio_chip structure associated to this GPIO controller
45 struct gpio_chip gc;
65 raw_spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
72 raw_spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
130 tb10x_gpio->gc.label =
132 if (!tb10x_gpio->gc.label)
140 ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
151 tb10x_gpio->gc.base = -1;
152 tb10x_gpio->gc.parent = dev;
153 tb10x_gpio->gc.owner = THIS_MODULE;
158 tb10x_gpio->gc.ngpio = ngpio;
159 tb10x_gpio->gc.request = gpiochip_generic_request;
160 tb10x_gpio->gc.free = gpiochip_generic_free;
162 ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
171 struct irq_chip_generic *gc;
177 tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
187 tb10x_gpio->gc.ngpio,
194 tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
200 gc = tb10x_gpio->domain->gc->gc[0];
201 gc->reg_base = tb10x_gpio->base;
202 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
203 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
204 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
205 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
206 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
207 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
208 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
222 if (tb10x_gpio->gc.to_irq) {
223 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
224 BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
225 kfree(tb10x_gpio->domain->gc);