drivers/gpio/gpio-sch.c

50 static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
55 	if (gpio >= sch->resume_base) {
56 		gpio -= sch->resume_base;
63 static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
65 	if (gpio >= sch->resume_base)
66 		gpio -= sch->resume_base;
70 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
75 	offset = sch_gpio_offset(sch, gpio, reg);
76 	bit = sch_gpio_bit(sch, gpio);
78 	reg_val = !!(ioread8(sch->regs + offset) & BIT(bit));
83 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
89 	offset = sch_gpio_offset(sch, gpio, reg);
90 	bit = sch_gpio_bit(sch, gpio);
92 	reg_val = ioread8(sch->regs + offset);
99 	iowrite8(reg_val, sch->regs + offset);
104 	struct sch_gpio *sch = gpiochip_get_data(gc);
107 	spin_lock_irqsave(&sch->lock, flags);
108 	sch_gpio_reg_set(sch, gpio_num, GIO, 1);
109 	spin_unlock_irqrestore(&sch->lock, flags);
115 	struct sch_gpio *sch = gpiochip_get_data(gc);
117 	return sch_gpio_reg_get(sch, gpio_num, GLV);
122 	struct sch_gpio *sch = gpiochip_get_data(gc);
125 	spin_lock_irqsave(&sch->lock, flags);
126 	sch_gpio_reg_set(sch, gpio_num, GLV, val);
127 	spin_unlock_irqrestore(&sch->lock, flags);
133 	struct sch_gpio *sch = gpiochip_get_data(gc);
136 	spin_lock_irqsave(&sch->lock, flags);
137 	sch_gpio_reg_set(sch, gpio_num, GIO, 0);
138 	spin_unlock_irqrestore(&sch->lock, flags);
155 	struct sch_gpio *sch = gpiochip_get_data(gc);
157 	if (sch_gpio_reg_get(sch, gpio_num, GIO))
176 	struct sch_gpio *sch = gpiochip_get_data(gc);
198 	spin_lock_irqsave(&sch->lock, flags);
200 	sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
201 	sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
205 	spin_unlock_irqrestore(&sch->lock, flags);
213 	struct sch_gpio *sch = gpiochip_get_data(gc);
217 	spin_lock_irqsave(&sch->lock, flags);
218 	sch_gpio_reg_set(sch, gpio_num, GTS, 1);
219 	spin_unlock_irqrestore(&sch->lock, flags);
224 	struct sch_gpio *sch = gpiochip_get_data(gc);
227 	spin_lock_irqsave(&sch->lock, flags);
228 	sch_gpio_reg_set(sch, gpio_num, GGPE, val);
229 	spin_unlock_irqrestore(&sch->lock, flags);
262 	struct sch_gpio *sch = context;
263 	struct gpio_chip *gc = &sch->chip;
270 	spin_lock_irqsave(&sch->lock, flags);
272 	core_status = ioread32(sch->regs + CORE_BANK_OFFSET + GTS);
273 	resume_status = ioread32(sch->regs + RESUME_BANK_OFFSET + GTS);
275 	spin_unlock_irqrestore(&sch->lock, flags);
277 	pending = (resume_status << sch->resume_base) | core_status;
278 	for_each_set_bit(offset, &pending, sch->chip.ngpio)
292 	struct sch_gpio *sch = data;
294 	acpi_disable_gpe(NULL, sch->gpe);
295 	acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
298 static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
300 	struct device *dev = sch->chip.parent;
303 	status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
304 					  sch->gpe_handler, sch);
307 			sch->gpe, acpi_format_exception(status));
311 	status = acpi_enable_gpe(NULL, sch->gpe);
314 			sch->gpe, acpi_format_exception(status));
315 		acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
319 	return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
326 	struct sch_gpio *sch;
331 	sch = devm_kzalloc(dev, sizeof(*sch), GFP_KERNEL);
332 	if (!sch)
343 	sch->regs = regs;
345 	spin_lock_init(&sch->lock);
346 	sch->chip = sch_gpio_chip;
347 	sch->chip.label = dev_name(dev);
348 	sch->chip.parent = dev;
352 		sch->resume_base = 10;
353 		sch->chip.ngpio = 14;
360 		sch_gpio_reg_set(sch, 8, GEN, 1);
361 		sch_gpio_reg_set(sch, 9, GEN, 1);
366 		sch_gpio_reg_set(sch, 13, GEN, 1);
370 		sch->resume_base = 5;
371 		sch->chip.ngpio = 14;
375 		sch->resume_base = 21;
376 		sch->chip.ngpio = 30;
380 		sch->resume_base = 2;
381 		sch->chip.ngpio = 8;
388 	girq = &sch->chip.irq;
397 	sch->gpe = GPE0E_GPIO;
398 	sch->gpe_handler = sch_gpio_gpe_handler;
400 	ret = sch_gpio_install_gpe_handler(sch);
404 	return devm_gpiochip_add_data(dev, &sch->chip, sch);